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74AVC16836DGG PDF даташит

Спецификация 74AVC16836DGG изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «20-bit registered driver with inverted register enable 3-State».

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Номер произв 74AVC16836DGG
Описание 20-bit registered driver with inverted register enable 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74AVC16836DGG Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74AVC16836
20-bit registered driver with inverted
register enable (3-State)
Preliminary specification
Replaces datasheet 74AVC16836/74AVCH16836 dated 1998 Dec 07
1999 Jul 23
Philips
Semiconductors









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74AVC16836DGG Даташит, Описание, Даташиты
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Preliminary specification
74AVC16836
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Power off disables 74AVC16836 outputs, permitting Live Insertion
DESCRIPTION
The 74AVC16836 is a 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
PIN CONFIGURATION
OE
Y0
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
Y19
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 CP
55 A0
54 A1
53 GND
52 A2
51 A3
50 VCC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 VCC
34 A16
33 A17
32 GND
31 A18
30 A19
29 LE
SH00159
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
tPHL/tPLH
Propagation delay
An to Yn
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.6
2.0
1.7
3.0
2.4
2.0
CI Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs enabled
Output disabled
5.0
25
6
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74AVC16836 DGG
DRAWING
NUMBER
SOT364-1
1999 Jul 23
2









No Preview Available !

74AVC16836DGG Даташит, Описание, Даташиты
Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Preliminary specification
74AVC16836
PIN DESCRIPTION
PIN NUMBER
28
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
20, 21, 23, 24, 26, 27
4, 11, 18, 25, 32, 35, 39,
46, 53
7, 22, 35, 50
1
29
56
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
31, 30
SYMBOL NAME AND FUNCTION
NC No connection
Y0 to Y19 Data outputs
GND
VCC
OE
LE
CP
Ground (0V)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
A0 to A19 Data inputs
LOGIC SYMBOL
OE
CP
LE
A0 D
LE Y0
CP
TO THE 19 OTHER CHANNELS
SH00163
LOGIC SYMBOL (IEEE/IEC)
OE 1
CP 56
LE 29
Y0 2
Y1 3
Y2 5
Y3 6
Y4 8
Y5 9
Y6 10
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
Y13 19
Y14 20
Y15 21
Y16 23
Y17 24
Y18 26
Y19 27
EN1
2C3
C3
G2
1 1 3D
55 A0
54 A1
52 A2
51 A3
49 A4
48
A5
47
A6
45 A7
44 A8
43
A9
42
A10
41
A11
40
A12
38 A13
37 A14
36 A15
34 A16
33 A17
31 A18
30 A19
SH00160
FUNCTION TABLE
INPUTS
OE LE CP
OUTPUTS
A
HXXX
Z
LLXL
L
LLX
LH
LH
L HH
LHL
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
= LOW-to-HIGH level transition
H
L
H
X
X
H
L
H
Y01
Y02
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
1999 Jul 23
3










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