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74F112 PDF даташит

Спецификация 74F112 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Dual JK Negative Edge-Triggered Flip-Flop».

Детали детали

Номер произв 74F112
Описание Dual JK Negative Edge-Triggered Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74F112 Даташит, Описание, Даташиты
April 1988
Revised July 1999
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q
and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F112SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F112PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009472
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74F112 Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1, J2, K1, K2 Data Inputs
CP1, CP2
Clock Pulse Inputs (Active Falling Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
SD1, SD2
Direct Set Inputs (Active LOW)
Q1, Q2, Q1, Q2 Outputs
1.0/1.0
1.0/4.0
1.0/5.0
1.0/5.0
50/33.3
20 µA/0.6 mA
20 µA/2.4 mA
20 µA/3.0 mA
20 µA/3.0 mA
1 mA/20 mA
Truth Table
Inputs
Outputs
SD CD CP J K
L H X XX
Q
H
Q
L
H L X XX L H
L
L
X XX H
H
H H
H H
h h Q0 Q0
lh L
H
H H
hl H L
H H
l l Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F112 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
0.5V to +7.0V
0.5V to +7.0V
Input Current (Note 2)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
0.5V to VCC
0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH Input HIGH Voltage
2.0
VIL Input LOW Voltage
VCD Input Clamp Diode Voltage
VOH Output HIGH
10% VCC
2.5
Voltage
5% VCC
2.7
VOL Output LOW
10% VCC
Voltage
0.8
1.2
0.5
V
V
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min IIN = −18 mA
Min IOH = −1 mA
IOH = −1 mA
Min IOL = 20 mA
IIH Input HIGH
Current
5.0 µA Max VIN = 2.7V
IBVI Input HIGH Current
Breakdown Test
7.0 µA Max VIN = 7.0V
ICEX
Output HIGH
Leakage Current
50 µA Max VOUT = VCC
VID Input Leakage
Test
4.75
V 0.0 IID = 1.9 µA
All other pins grounded
IOD Output Leakage
Circuit Current
3.75
µA
0.0 VIOD = 150 mV
All other pins grounded
IIL Input LOW Current
IOS
ICCH
ICCL
Output Short-Circuit Current
Power Supply Current
Power Supply Current
0.6
VIN = 0.5V (Jn, Kn)
2.4 mA Max VIN = 0.5V (CPn)
3.0
VIN = 0.5V (CDn, SDn)
60 150 mA Max VOUT = 0V
12 19 mA Max VO = HIGH
12 19 mA Max VO = LOW
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