74F113 PDF даташит
Спецификация 74F113 изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Dual JK Negative Edge-Triggered Flip-Flop». |
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Детали детали
Номер произв | 74F113 |
Описание | Dual JK Negative Edge-Triggered Flip-Flop |
Производители | Fairchild Semiconductor |
логотип |
6 Pages
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April 1988
Revised July 1999
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to SD sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number Package Number
Package Description
74F113SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F113SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F113PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009473
www.fairchildsemi.com
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Unit Loading/Fan Out
Pin Names
Description
J1, J2, K1, K2
CP1, CP2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
U.L.
HIGH/LOW
1.0/1.0
1.0/4.0
1.0/5.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
−1 mA/20 mA
Inputs
Outputs
SD CP J K Q
Q
L X XX H L
H h h Q0 Q0
H l h L H
H h l H L
H l l Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage level
] = HIGH-to-LOW Clock Transition
X = Immaterial
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1)
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Junction Temperature under Bias
−55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
−0.5V to VCC
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
ICEX
VID
IOD
IIL
IOZH
IOZL
IOS
ICC
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
10% VCC
5% VCC
10% VCC
2.0
2.5
2.7
4.75
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
−60
0.8
−1.2
0.5
V
V
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min IIN = −18 mA
Min IOH = −1 mA
IOH = −1 mA
Min IOL = 20 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
50
µA
Max
VOUT = VCC
V 0.0 IID = 1.9 µA
All Other Pins Grounded
3.75
µA
0.0 VIOD = 150 mV
All Other Pins Grounded
−0.6
VIN = 0.5V (Jn, Kn)
−2.4 mA Max VIN = 0.5V (CPn)
−3.0
VIN = 0.5V (SDn)
50 µA Max VOUT = 2.7V
−50 µA Max VOUT = 0.5V
−150 mA Max VOUT = 0V
12 19 mA Max
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