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74F161ASJ PDF даташит

Спецификация 74F161ASJ изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Synchronous Presettable Binary Counter».

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Номер произв 74F161ASJ
Описание Synchronous Presettable Binary Counter
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74F161ASJ Даташит, Описание, Даташиты
April 1988
Revised July 1999
74F161A • 74F163A
Synchronous Presettable Binary Counter
General Description
The 74F161A and 74F163A are high-speed synchronous
modulo-16 binary counters. They are synchronously pre-
settable for application in programmable dividers and have
two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multi-stage
counters. The 74F161A has an asynchronous Master-
Reset input that overrides all other inputs and forces the
outputs LOW. The 74F163A has a Synchronous Reset
input that overrides counting and parallel loading and
allows the outputs to be simultaneously reset on the rising
edge of the clock. The 74F161A and 74F163A are high-
speed versions of the 74F161 and 74F163.
Features
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count frequency of 120 MHz
Ordering Code:
Order Number Package Number
Package Description
74F161ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F161ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F163ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F163ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F161A
74F163A
© 1999 Fairchild Semiconductor Corporation DS009486
www.fairchildsemi.com









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74F161ASJ Даташит, Описание, Даташиты
Logic Symbols
74F161A
IEEE/IEC
74F163A
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Pin Names
Description
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP Clock Pulse Input (Active Rising Edge)
MR (74F161A) Asynchronous Master Reset Input (Active LOW)
SR (74F163A) Synchronous Reset Input (Active LOW)
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Q0–Q3
TC
Flip-Flop Outputs
Terminal Count Output
U.L.
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/1.2 mA
1 mA/20 mA
1 mA/20 mA
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74F161ASJ Даташит, Описание, Даташиты
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous reset (74F161A), synchronous reset
(74F163A), parallel load, count-up and hold. Five control
inputs—Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-
lel (CEP) and Count Enable Trickle (CET)—determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchro-
nously forces all outputs LOW. A LOW signal on SR over-
rides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchro-
nous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
SR
(Note 1)
PE
CET
CE
P
Action on the Rising
Clock Edge ( )
L X X X Reset (Clear)
H L X X Load (PnQn)
H H H H Count (Increment)
H H L X No Change (Hold)
H H X L No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: For 74F163A only
State Diagram
Block Diagram
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