74F175A PDF даташит
Спецификация 74F175A изготовлена «NXP Semiconductors» и имеет функцию, называемую «Quad D flip-flop». |
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Детали детали
Номер произв | 74F175A |
Описание | Quad D flip-flop |
Производители | NXP Semiconductors |
логотип |
10 Pages
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INTEGRATED CIRCUITS
74F175*, 74F175A
Quad D flip-flop
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
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Philips Semiconductors
Quad D flip-flop
Product specification
74F175A
FEATURES
• Four edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous Master Reset
• True and complementary outputs
• Industrial temperature range available (–40°C to +85°C)
• PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with
individual D inputs and both Q and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR input. The device is useful
for applications where both true and complementary outputs are
required, and the CP and MR are common to all storage elements.
PIN CONFIGURATION
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
SF00718
TYPE
74F175A
TYPICAL fmax
160MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
22mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE PKG. DWG. #
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP
74F175AN
SOT38-4
16-pin plastic SO
74F175AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
D0 – D3 Data inputs
MR Master reset input (active–Low)
CP Clock input (active rising edge)
Q0–Q3 True outputs
Q0–Q3 Complementary outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F175A
74F175A
74F175A
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
1996 Mar 12
2 853–0047 16555
No Preview Available ! |
Philips Semiconductors
Quad D flip-flop
Product specification
74F175A
LOGIC SYMBOL
9
1
VCC = Pin 16
GND = Pin 8
4 5 12 13
D0 D1 D2 D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
2 3 7 6 10 11 15 14
SF00719
IEC/IEEE SYMBOL
1
9
4
5
12
13
R
C1
1D
2
3
7
6
10
11
15
14
SF00720
LOGIC DIAGRAM
CP 9
VCC = Pin 16
GND = Pin 8
1
MR
D0 D1 D2 D3
4 5 12 13
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP Q
RD
32
Q0 Q0
67
Q1 Q1
11 10
Q2 Q2
14 15
Q3 Q3
SF00721
FUNCTION TABLE
INPUTS
MR CP Dn
LXX
H↑ h
H↑
I
OUTPUTS
Qn Qn
LH
HL
LH
OPERATING
MODE
Reset (clear)
Load “1”
Load “0”
H = High voltage level
h = High state must be present one setup time before the
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time before the
Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
IOUT Current applied to output in Low output state
Tamb Operating free air temperature range
Commercial range
Industrial range
Tstg Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
1996 Mar 12
3
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