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PDF 74ABT652CMTC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT652CMTC | |
| Descripción | Octal Transceivers and Registers with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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November 1992
Revised January 1999
74ABT652
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT652 consists of bus transceiver circuits with D-
type flip-flops and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT652CSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT652CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT652CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Names
Description
A0–A7
B0–B7
CPAB, CPBA
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
SAB, SBA
Select Inputs
OEAB, OEBA Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation DS011512.prf
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
(SOIC package)
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.6 0.8 V 5.0 TA = 25°C (Note 7)
VOLV
Quiet Output Minimum Dynamic VOL
−1.2
−0.9
V 5.0 TA = 25°C (Note 7)
VOHV
Minimum HIGH Level Dynamic Output Voltage 2.5
3.0
V 5.0 TA = 25°C (Note 8)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V 5.0 TA = 25°C (Note 9)
VILD Maximum LOW Level Dynamic Input Voltage
0.8 0.4 V 5.0 TA = 25°C (Note 9)
Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 9: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
Symbol
Parameter
fmax Max Clock Frequency
tPLH Propagation Delay
tPHL Clock to Bus
tPLH Propagation Delay
tPHL Bus to Bus
tPLH Propagation Delay
tPHL SBA or SAB to An to Bn
tPZH
Enable Time
tPZL OEBA or OEAB to An or Bn
tPHZ Disable Time
tPLZ OEBA or OEAB to An or Bn
Min
200
1.7
1.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TA = +25°C
VCC = +5.0V
CL = 50 pF
Typ
3.0
3.4
2.6
3.0
3.0
3.4
3.3
3.7
3.7
3.3
Max
4.9
4.9
4.5
4.5
5.0
5.0
5.5
5.5
6.0
6.0
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
200
1.7 4.9
1.7 4.9
1.5 4.5
1.5 4.5
1.5 5.0
1.5 5.0
1.5 5.5
1.5 5.5
1.5 6.0
1.5 6.0
Units
MHz
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74ABT652CMTC.PDF ] | |
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