DataSheet26.com

74ABT652CSC PDF даташит

Спецификация 74ABT652CSC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Octal Transceivers and Registers with 3-STATE Outputs».

Детали детали

Номер произв 74ABT652CSC
Описание Octal Transceivers and Registers with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

10 Pages
scroll

No Preview Available !

74ABT652CSC Даташит, Описание, Даташиты
November 1992
Revised January 1999
74ABT652
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT652 consists of bus transceiver circuits with D-
type flip-flops and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to HIGH
logic level. Output Enable pins (OEAB, OEBA) are pro-
vided to control the transceiver function.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT652CSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT652CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT652CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Names
Description
A0–A7
B0–B7
CPAB, CPBA
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
SAB, SBA
Select Inputs
OEAB, OEBA Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation DS011512.prf
www.fairchildsemi.com









No Preview Available !

74ABT652CSC Даташит, Описание, Даташиты
Truth Table
Inputs
Inputs/Outputs (Note 1)
Operating Mode
OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7
L H H or L H or L X X Input
Input
Isolation
 L H
XX
Store A and B Data
X H
H or L X
X Input
Not Specified Store A, Hold B
 H H
X X Input
Output
Store A in Both Registers
L X H or L
X X Not Specified Input
Hold A, Store B
 L L
X X Output
Input
Store B in Both Registers
L L X X X L Output
Input
Real-Time B Data to A Bus
L L X H or L X H
Store B Data to A Bus
H H X X L X Input
Output
Real-Time A Data to B Bus
H H H or L X H X
Stored A Data to B Bus
H L H or L H or L H H Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the ABT652.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2









No Preview Available !

74ABT652CSC Даташит, Описание, Даташиты
Note A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA SAB SBA
L L X X XL
Note C: Storage
OEAB OEBA CPAB CPBA SAB SBA
H H X X LX
Note D: Transfer Storage
Data to A or B
OEAB OEBA
XH
LX
LH
CPAB CPBA SAB SBA
 X XX
X X X
XX
OEAB OEBA CPAB CPBA SAB SBA
H L H or L H or L H H
FIGURE 1.
3 www.fairchildsemi.com










Скачать PDF:

[ 74ABT652CSC.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74ABT652CSCOctal Transceivers and Registers with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск