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74ABTH162240 PDF даташит

Спецификация 74ABTH162240 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «16-bit inverting buffer/driver with 30ohm series termination resistors».

Детали детали

Номер произв 74ABTH162240
Описание 16-bit inverting buffer/driver with 30ohm series termination resistors
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ABTH162240 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ABT161543
74ABTH161543
16-bit latched transceiver with
dual enable and master reset (3-State)
Product specification
Supersedes data of 1995 Sep 18
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors









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74ABTH162240 Даташит, Описание, Даташиты
Philips Semiconductors
16-bit latched transceiver with dual enable
and master reset (3-State)
Product specification
74ABT161543
74ABTH161543
FEATURES
Two 8-bit octal transceivers with D-type latch
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Multiple VCC and GND pins minimize switching noise
Back-to-back registers for storage
Separate controls for data flow in each direction
74ABTH161543 incorporates Bus hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Same function as ABT16543 except for additional Master Reset
control pins
DESCRIPTION
The 74ABT161543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT161543 16-bit registered transceiver contains two sets
of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB, nLEBA) and Output
Enable (nOEAB, nOEBA) inputs are provided for each register to
permit independent control of data transfer in either direction. Master
reset (MR) clears all registers simultaneously and sets them Low.
The outputs are guaranteed to sink 64mA.
Two options are available, 74ABT161543 which does not have the
Bus hold feature and 74ABTH161543 which inorporates the Bus
hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
CI/O
ICCZ
ICCL
Propagation delay
nAx to nBx
Input capacitance
I/O capacitance
Quiescent supply current
ORDERING INFORMATION
PACKAGES
56-pin plastic SSOP Type III
56-pin plastic TSSOP Type II
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VO = 0V or VCC; 3-State
Outputs disabled; VCC = 5.5V
Outputs low; VCC = 5.5V
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
ORDER CODE
BT161543DL
BT161543DGG
TYPICAL
2.5
2.2
3
7
500
9
UNIT
ns
pF
pF
µA
mA
DRAWING NUMBER
SOT371-1
SOT364-1
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT161543 DL
74ABT161543 DGG
74ABTH161543 DL
74ABTH161543 DGG
NORTH AMERICA
BT161543 DL
BT161543 DGG
BH161543 DL
BH161543 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1, 56
28, 29
3, 54
26, 31
2, 55
27, 30
4, 25
11, 18, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
1EAB, 1EBA,
2EAB, 2EBA
1LEAB, 1LEBA,
2LEAB, 2LEBA
MRab, MRba
GND
VCC
NAME AND FUNCTION
Data inputs/outputs
Data inputs/outputs
A to B / B to A Output Enable inputs (active-Low)
A to B / B to A Enable inputs (active-Low)
A to B / B to A Latch Enable inputs (active-Low)
Master reset
Ground (0V)
Positive supply voltage
1998 Feb 27
2 853-1798 19026









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74ABTH162240 Даташит, Описание, Даташиты
Philips Semiconductors
16-bit latched transceiver with dual enable
and master reset (3-State)
Product specification
74ABT161543
74ABTH161543
LOGIC SYMBOL (IEEE/IEC)
MRab
1OEAB
1EAB
1LEAB
2OEAB
2EAB
2LEAB
MRba
1OEBA
1EBA
1LEBA
2OEBA
2EBA
2LEBA
4
1
3
2
28
26
27
25
56
54
55
29
31
30
1A0 5
1A1 6
1A2 8
1A3 9
1A4 10
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
2A3 19
2A4 20
2A5 21
2A6 23
2A7 24
R6/R12
2EN4
G2
2C6
8EN10
G8
8C12
R5/R11
1EN3
G1
1C5
7EN9
G7
7C11
3
6D
5D
4
9 11D
12D 10
52 1B0
51 1B1
49 1B2
48 1B3
47 1B4
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
38 2B3
37 2B4
36 2B5
34 2B6
33 2B7
SH00060
PIN CONFIGURATION
1OEAB 1
1LEAB 2
1EAB 3
MRab 4
1A0 5
1A1 6
VCC 7
1A2 8
1A3 9
1A4 10
GND 11
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
GND 18
2A3 19
2A4 20
2A5 21
VCC 22
2A6 23
2A7 24
MRba 25
2EAB 26
2LEAB 27
2OEAB 28
56 1OEBA
55 1LEBA
54 1EBA
53 GND
52 1B0
51 1B1
50 VCC
49 1B2
48 1B3
47 1B4
46 GND
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
39 GND
38 2B3
37 2B4
36 2B5
35 VCC
34 2B6
33 2B7
32 GND
31 2EBA
30 2LEBA
29 2OEBA
SH00061
1998 Feb 27
3










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