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74ABTL3205BB PDF даташит

Спецификация 74ABTL3205BB изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «10-bit BTL transceiver with registers».

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Номер произв 74ABTL3205BB
Описание 10-bit BTL transceiver with registers
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ABTL3205BB Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ABTL3205
10-bit BTL transceiver with registers
Product specification
1995 Jun 16
Philips
Semiconductors









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74ABTL3205BB Даташит, Описание, Даташиты
Philips Semiconductors
10-bit BTL transceiver with registers
Product specification
74ABTL3205
FEATURES
10-bit BTL transceiver
Drives heavily loaded backplanes with equivalent load
impedances down to 10 ohms
High drive 100mA BTL open collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Controlled output ramp and multiple GND pins minimize ground
bounce
Tight output skew (0.5nsec typical)
Glitch-free power up/down operation
Low ICC current
Supports live insertion
High density packaging
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
This transceiver is a 10 bit bidirectional transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good margins by limiting
the switching threshold to a narrow region centered at 1.55V.
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading (<6pF) by placing an internal series
diode on the drivers. BTL also provides incident wave switching, a
necessity for high performance backplanes.
To support live insertion, OEB is held Low during power on/off cycles
to insure glitch free B port drivers. Proper bias for B port drivers
during live insertion is provided by the BIAS V pin when at a 5V level
while VCC is Low. The BIAS V pin is a low current input which will
reverse bias the BTL driver series Schottky diode, and also bias the
B port output pins to a voltage between 1.62V and 2.1V. This bias
function is in accordance with IEEE BTL standard 1194.1. If live
insertion is not a requirement, the BIAS V pin should be tied to a
VCC pin.
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package. The LOGIC VCC and BUS VCC pins are also isolated
internally to minimize noise and may be externally decoupled
separately or simply tied together.
This transceiver function is intended to operate in a half-duplex
mode. Low current in standby mode is obtained by powering down
unused circuitry. Likewise, transmit circuitry is powered down when
in receive mode and receive circuitry is powered down while in
transmit mode.
QUICK REFERENCE DATA
SYMBOL
tPLH Propagation delay
tPHL
An to Bn
tPLH Propagation delay
tPHL
Bn to An
COB Output capacitance (B0 - B8) only)
IOL Output current (B0 - B8) only)
ICC Supply current
PARAMETER
Standby
An to Bn
Bn to An
TYPICAL
3.3
3.7
3.6
3.5
6
100
1
7
18
UNIT
ns
ns
pF
mA
mA
ORDERING INFORMATION
PACKAGES
52-PIN PQFP
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABTL3205 BB
NORTH AMERICA
74ABTL3205 BB
DWG NUMBER
SOT379-1
1995 Jun 16
2 853-1802 15352









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74ABTL3205BB Даташит, Описание, Даташиты
Philips Semiconductors
10-bit BTL transceiver with registers
Product specification
74ABTL3205
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
TTL Gnd
A0
1
2
A1 3
TTL GND 4
A2 5
A3 6
TTL GND 7
AClk2 8
TTL GND 9
A4 10
A5 11
TTL GND 12
A6 13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
BUS GND
B0
B1
BUS GND
B2
B3
BUS GND
BClk2
BUS GND
B4
B5
BUS GND
B6
PIN DESCRIPTION
SYMBOL
FUNCTION
OEA1
Output enable data receiver group 1
OEA2
Output enable data receiver group 2
OEB
Output enable data transmitter
IEA Output enable clock and framepulse receiver
M/S Master/Slave select:
L: Master, enable clock transmitter
H: Slave, disable clock transmitter
Mode
Low:
High:
Data through mode
Registered data mode
Power Up
Power up mode, held low during power up to
disable clock and data transmitters
Recmode
Enables receiver
Tranmode
Enables transmitter
AClk1
Clock or data path
AClkln
IEA = H Input for busclock
IEA = L Output for busclock
A0..A3
data group 1
AClk2
Clock or data path
AFPIn
Alternate data path
APAR
Alternate data path
A4..A7
data group 2
BClk1
Clock or data path
B0..B3
data group 1
BClk2
Clock or data path
B4..B7
data group 2
1995 Jun 16
3
SA00138
ASSERTION
Low
Low
Low
Low
I/O
Input
Input
Input
Input
Input
LOGIC
TTL
TTL
TTL
TTL
TTL
Input
TTL
Low
High
High
Input
Input
Input
I/O
I/O
TTL
TTL
TTL
TTL
TTL
I/O
I/O
Output
Input
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
BTL
BTL
BTL
BTL










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