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PDF 74AC125M Data sheet ( Hoja de datos )

Número de pieza 74AC125M
Descripción QUAD BUS BUFFERS 3-STATE
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



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No Preview Available ! 74AC125M Hoja de datos, Descripción, Manual

74AC125
QUAD BUS BUFFERS (3-STATE)
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The AC125 is an high-speed CMOS QUAD BUS
BUFFERS fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology. It is ideal for low power applications
maintaining high speed operation similar to
PRELIMINARY DATA
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC125B
74AC125M
equivalent Bipolar Schottky TTL.
These devices require the same 3-STATE control
input G to be taken high to make the output go in
to the high impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
1/8

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74AC125M pdf
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74AC125
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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