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PDF 74AC161 Data sheet ( Hoja de datos )
| Número de pieza | 74AC161 | |
| Descripción | Synchronous Presettable Binary Counter | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised November 1999
74AC161 • 74ACT161
Synchronous Presettable Binary Counter
General Description
The AC/ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
Features
s ICC reduced by 50%
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count rate of 125 MHz
s Outputs source/sink 24 mA
s ACT161 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC161SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC161PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT161SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT161MTC
MTC16
16-Lead Thin Shrwinwkw.DSamtaSahlleeOt4uUt.lcinome Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT161PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
CEP
CET
CP
MR
P0–P3
PE
Q0–Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009931
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACT
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5 2.0
2.0
5.5 1.5 2.0
2.0
4.5 1.5 0.8
0.8
5.5 1.5 0.8
0.8
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input
Leakage Current
5.5
±0.1
ICCT
IOLD
IOHD
ICC
Maximum
ICC/Input
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5 4.0
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
±1.0
1.5
75
−75
40.0
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 5)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 5)
µA VI = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
AC Electrical Characteristics for AC
Symbol
Parameter
fMAX
Maximum Count
Frequency
tPLH Propagation Delay CP to Qn
(PE Input HIGH or LOW)
tPHL Propagation Delay CP to Qn
(PE Input HIGH or LOW)
tPLH Propagation Delay
CP to TC
tPHL Propagation Delay
CP to TC
tPLH Propagation Delay
CET to TC
tPHL Propagation Delay
CET to TC
tPHL Propagation Delay
MR to Qn
tPHL Propagation Delay
MR to TC
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 7)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
70 111
110 167
2.0 7.0 12
1.5 5.0 9.0
1.5 7.0 12
1.5 5.0 9.5
3.0 9 15
2.0 6 10.5
3.5 8.5 14
2.0 6.5 11
2.0 5.5 9.5
1.5 3.5 6.5
2.5 6.5 11
2.0 5 8.5
2.0 6.5 12
1.5 5.5 9.5
3.5 10 15
2.5 8.5 13
TA = −40°C to +85°C
CL = 50 pF
Min Max
60
95
1.5 13.5
1.0 9.5
1.5 13
1.5 10
2.5 16.5
1.5 11.5
2.5 15.5
2.0 11.5
1.5 11
1.0 7.5
2.0 12.5
1.5 9.5
1.5 13.5
1.5 10
3.0 17.5
2.5 13.5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74AC161.PDF ] | |
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