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PDF 74AC174 Data sheet ( Hoja de datos )
| Número de pieza | 74AC174 | |
| Descripción | HEX D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74AC174
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
s HIGH SPEED:
fMAX =125 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
B
(Plastic Package)
M
(Micro Package)
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
ORDER CODES :
74AC174B
74AC174M
TTL.
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
All inputs and outputs are equipped with
DESCRIPTION
protection circuits against static discharge, giving
The AC174 is an high-speed CMOS HEX themwww.DataSheet4U.com 2KV ESD immunity and transient excess
D-TYPE FLIP FLOP WITH CLEAR fabricated voltage.
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to eqivalent Bipolar Schottky
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
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1 page  
74AC174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL CK to Q
tPLH Propagation Delay Time
tPHL CLR to Q
twL CLR pulse Width, LOW
tw CK pulse Width
ts Setup Time Q to CK HIGH
or LOW
th Hold Time Q to CK HIGH
or LOW
tREM Recovery Time CLR to CK
fMAX Maximum Clock Frequency
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
1.5 8.5 11.0
12.0
1.5 6.0 8.0
9.0
1.5 9.0 11.0
12.0
1.5 7.0 9.0
10.0
1.0 5.5
7.0
1.0 5.0
5.0
1.0 5.5
7.0
1.0 5.0
5.0
2.5 6.5
7.0
2.0 5.0
5.5
1.0 3.0
3.0
0.5 3.0
3.0
0 2.5
2.5
0 2.0
2.0
90 100
70
100 125
100
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0 fIN = 10 MHz
TBD
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN +ICC/n (per circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74AC174.PDF ] | |
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