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PDF 74AC377MTC Data sheet ( Hoja de datos )
| Número de pieza | 74AC377MTC | |
| Descripción | Octal D-Type Flip-Flop with Clock Enable | |
| Fabricantes | Fairchild Semiconductor | |
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November 1988
Revised November 1999
74AC377 • 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s ICC reduced by 50%
s Ideal for addressable register applications
s Clock enable for address and data synchronization
applications
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Outputs source/sink 24 mA
s See 273 for master reset version
s See 373 for transparent latch version
s See 374 for 3-STATE version
s ACT377 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC377SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC377SJ
74AC377MTC
M20D
MTC20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
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20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC377PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT377SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT377SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT377PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CE
Q0–Q7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009961
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tS Setup Time, HIGH or LOW
CE to CP
tH Hold Time, HIGH or LOW
CE to CP
tW CP Pulse Width
HIGH or LOW
Note 8: Voltage Range 3.3 is 3.0V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
3.5 5.5
6.0
2.5 4.0
4.5
−2.0
0
0
−1.0
1.0
1.0
4.0 6.0
7.5
2.5 4.0
4.5
−3.5
0
0
−2.0
1.0
1.0
3.5 5.5
6.0
2.5 4.0
4.5
AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CP to Qn
tPHL Propagation Delay
CP to Qn
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
Min
140
5.0 3.0
5.0 3.5
AC Operating Requirements for ACT
TA = +25°C
CL = 50 pF
Typ
175
6.5
7.0
Max
9.0
10.0
TA = −40°C to +85°C
CL = 50 pF
Min Max
125
2.5 10.0
2.5 11.0
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tS Setup Time, HIGH or LOW
CE to CP
tH Hold Time, HIGH or LOW
CE to CP
tW CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
5.0
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
2.5 4.5
5.5
−1.0
1.0
1.0
2.5 4.5
5.5
−1.0
1.0
1.0
2.0 4.0
4.5
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5
90.0
pF VCC = OPEN
pF VCC = 5.0V
Units
ns
ns
ns
ns
ns
Units
MHz
ns
ns
Units
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74AC377MTC.PDF ] | |
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