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PDF 74AC648 Data sheet ( Hoja de datos )
| Número de pieza | 74AC648 | |
| Descripción | Octal Transceiver/Register with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised August 2000
74AC648
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figure 1, Figure 2, Figure 3, and
Figure 4.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data transfers
s 3-STATE outputs
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Inverted data to output
Ordering Code:
Order Number Package Number
Package Description
74AC648SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC648SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
www.DataSheet4U.com
IEEE/IEC
Pin Descriptions
Pin Names
A0–A7
B0– B7
CPAB, CPBA
SAB, SBA
DIR, G
Description
Data Register A Inputs,
Data Register A 3-STATE Outputs
Data Register B Inputs,
Data Register B 3-STATE Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010133
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
VCC
Symbol
Parameter
(V)
(Note 6)
Min
tPLH Propagation Delay
Clock to Bus
3.3 1.5
5.0 1.5
tPHL Propagation Delay
Clock to Bus
3.3 1.5
5.0 1.5
tPLH Propagation Delay
Bus to Bus
3.3 1.5
5.0 1.5
tPHL Propagation Delay
Bus to Bus
3.3 1.5
5.0 1.5
tPLH Propagation Delay
3.3
SBA or SAB to An or Bn
5.0
(with An or Bn HIGH or LOW)
tPHL Propagation Delay
3.3
SBA or SAB to An or B n
5.0
(with An or Bn HIGH or LOW)
tPZH
Enable Time
3.3
G to An or Bn
5.0
tPZL Enable Time
3.3
G to An or Bn
5.0
tPHZ Disable Time
3.3
G to An or Bn
5.0
tPLZ Disable Time
3.3
G to An or Bn
5.0
tPZH
Enable Time
3.3
DIR to An or Bn
5.0
tPZL Enable Time
3.3
DIR to An or Bn
5.0
tPHZ Disable Time
3.3
DIR to An or Bn
5.0
tPLZ Disable Time
3.3
DIR to An or Bn
5.0
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TA = +25°C
CL = 50 pF
Typ
10.0
7.0
8.5
6.0
6.0
4.0
5.5
3.5
7.5
5.5
7.5
5.5
6.5
5.0
7.0
5.0
7.5
6.0
7.0
5.5
6.0
4.5
6.5
4.5
7.0
5.5
7.0
5.0
Max
15.5
11.0
13.5
10.5
10.0
7.0
9.0
7.5
12.5
9.0
12.5
9.5
11.0
8.0
11.0
8.0
12.0
10.0
11.5
9.0
12.5
9.5
13.0
9.0
11.5
9.0
13.5
9.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
1.5 17.0
1.5 12.0
1.5 14.5
1.5 11.5
1.5 11.0
1.0 7.5
1.5 10.0
1.0 8.0
1.5 14.0
1.5 10.0
1.5 14.0
1.5 10.5
1.0 11.5
1.0 9.0
1.0 12.5
1.0 9.0
1.0 13.0
1.0 11.0
1.0 12.5
1.0 10.0
1.0 14.0
1.0 10.5
1.5 14.5
1.0 10.5
1.0 13.5
1.0 10.0
1.5 15.0
1.0 10.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Operating Requirements
Symbol
Parameter
VCC
(V)
(Note 7)
tS Setup Time, HIGH or LOW,
Bus to Clock
3.3
5.0
tH Hold Time, HIGH or LOW,
Bus to Clock
tW Clock Pulse Width
HIGH or LOW
3.3
5.0
3.3
5.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
2.0 3.0
3.5
1.5 2.0
2.0
−1.5
0
0
−0.5
1.0
1.0
2.0 3.5
4.0
2.0 3.0
3.0
Units
ns
ns
ns
Capacitance
CIN
CPD
CI/O
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Input/Output Capacitance
Typ
4.5
65.0
15.0
Units
pF
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
VCC = 5.0V
5 www.fairchildsemi.com
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