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Спецификация 74AC821 изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «10-Bit D-Type Flip-Flop with 3-STATE Outputs». |
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Детали детали
Номер произв | 74AC821 |
Описание | 10-Bit D-Type Flip-Flop with 3-STATE Outputs |
Производители | Fairchild Semiconductor |
логотип |
8 Pages
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November 1988
Revised August 2000
74AC821 • 74ACT821
10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE
outputs arranged in a broadside pinout.
Features
s 3-STATE outputs for bus interfacing
s Noninverting outputs
s Outputs source/sink 24 mA
s TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC821SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC821SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT821SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT821MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT821SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
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IEEE/IEC
Pin Descriptions
Pin Names
D0–D9
O0–O9
OE
CP
Description
Data Inputs
Data Outputs
Output Enable Input
Clock Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010139
www.fairchildsemi.com
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Functional Description
The AC/ACT821 consists of ten D-type edge-triggered flip-
flops. The buffered Clock (CP) and buffered Output Enable
(OE) are common to all flip-flops. The flip-flops will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH CP transition.
With OE LOW the contents of the flip-flops are available at
the outputs. When OE is HIGH the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip-flops.
Function Table
OE
H
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
= LOW-to-HIGH Clock Transition
Logic Diagram
Inputs
CP
Internal Outputs
Function
DQ
O
LL
Z High Z
HH
Z High Z
LL
L Load
HH
H Load
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = − 0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
− 0.5V to + 7.0V
− 20 mA
+ 20 mA
− 0.5V to VCC + 0.5V
− 20 mA
+ 20 mA
− 0.5V to VCC + 0.5V
± 50 mA
± 50 mA
− 65°C to + 150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
0V to VCC
0V to VCC
− 40°C to + 85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5
2.1
2.1
4.5 2.25 3.15
3.15
5.5 2.75 3.85
3.85
3.0 1.5
0.9
0.9
4.5 2.25 1.35
1.35
5.5 2.75 1.65
1.65
3.0 2.99
2.9
2.9
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002
0.1
4.5 0.001
0.1
5.5 0.001
0.1
2.46
3.76
4.76
0.1
0.1
0.1
IIN (Note 4)
IOZ
Maximum Input Leakage Current
Maximum 3-STATE Current
3.0
4.5
5.5
5.5
5.5
0.36
0.36
0.36
± 0.1
±0.5
0.44
0.44
0.44
± 1.0
±5.0
IOLD
IOHD
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
75
−75
ICC (Note 4) Maximum Quiescent Supply Current 5.5
8.0 80.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions
VOUT = 0.1V
V or VCC − 0.1V
VOUT = 0.1V
V or VCC − 0.1V
V IOUT = − 50 µA
VIN = VIL or VIH
IOH = − 12 mA
V IOH = − 24 mA
IOH = − 24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
VI (OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
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