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PDF 74ACT138B Data sheet ( Hoja de datos )
| Número de pieza | 74ACT138B | |
| Descripción | 3 TO 8 LINE DECODER INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ACT138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT138 is an advanced high-speed CMOS 3
TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2G is held high, the decoding function is
inhibited and all the 8 outputs go to high.
PIN CONNECTION AND IEC LOGIC SYMBOLS
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT138B
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 1997
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1 page  
74ACT138
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
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5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ACT138B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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