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PDF 68901N04 Data sheet ( Hoja de datos )
| Número de pieza | 68901N04 | |
| Descripción | MULTI.FUNCTION PERIPHERAL | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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MK68901
MULTI–FUNCTION PERIPHERAL
. 8 INPUT/OUTPUT PINS
• Individually programmable direction
. • Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
• 8 Internal sources
• 8 External sources
• Individual source enable
• Individual source masking
• Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
• Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY PRO-
GRAMMABLE PRESCALING
• Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
• Two delay mode timers
. • Independent clock input
• Time out output option
SINGLE CHANNEL USART
• Full Duplex
• Asynchronous to 65 kbps
• Byte synchronous to 1 Mbps
• Internal/External baud rate generation
• DMA handshake signals
.. • Modem control
• Loop back mode
68000 BUS COMPATIBLE
48 PIN DIP OR 52 PIN PLCC
1
DPIP48
Figure 1 : Pin connections.
PLCC52
DESCRIPTION
The MK68901 MFP (Multi-Function Peripheral) is a
combination of many of the necessary peripheral
functions in a microprocessor system.
Included are :
Eight parallel I/O lines
Interrrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use of the MFP in a system can significantly re-
duce chip count, thereby reducing system cost. The
MFP is completely 68000 bus compatible, and 24 di-
rectly addressable internal registers provide the ne-
MFP
December 1988
1/33
1 page  
MK68901
There are 16 vector addresses generated internally
by the MK68901, one for each of the 16 interrupt
channels.
The Interrupt Control Registers (figure 8) provide
control of interrupt processing for all I/O facilities of
the MK68901. These registers allow the program-
Figure 5 : General Purpose I/O Registers.
mer to enable or disable any or all of the 16 inter-
rupts, providing masking for any interrupt, and pro-
vide access to the pending and in-service status of
the interrupt. Optional end-of-interrupt modes are
available under software control. All the interrupts
are prioritized as shown in figure 9.
Figure 6 : Interrupt Vector.
V000352
V000353
5/33
5 Page 
Figure 13 : Timer Data Registers (A, B, C, and D).
MK68901
Figure 14 : Timer C and D Register.
* Unused bi ts : read as zeros.
V000360
V000361
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 68901N04.PDF ] | |
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