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74163 Datasheet Download - Fairchild Semiconductor

Номер произв 74163
Описание Synchronous Presettable Binary Counter
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74163 Даташит, Описание, Даташиты
November 1988
Revised February 2000
74AC163 • 74ACT163
Synchronous Presettable Binary Counter
General Description
The AC/ACT163 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
Features
s ICC reduced by 50%
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count rate of 125 MHz
s Outputs source/sink 24 mA
s ACT163 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC163SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC163SJ
M16D
16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC163PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT163SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT163SJ
M16D
16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT163PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
CEP
CET
CP
SR
P0–P3
PE
Q0–Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
Terminal Count Output
© 2000 Fairchild Semiconductor Corporation DS009932
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74163 Даташит, Описание, Даташиты
Logic Symbols
IEEE/IEC
Mode Select Table
SR PE CET
LX X
HL
X
HH
H
HH
L
HH
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
CEP Action on the Rising
Clock Edge ( )
X Reset (Clear)
X Load (Pn Qn)
H Count (Increment)
X No Change (Hold)
L No Change (Hold)
Functional Description
The AC/ACT163 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
synchronous reset, parallel load, count-up and hold. Four
control inputs—Synchronous Reset (SR), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)—determine the mode of operation, as shown
in the Mode Select Table. A LOW signal on SR overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next
rising edge of CP. With PE and SR HIGH, CEP and CET
permit counting when both are HIGH. Conversely, a LOW
signal on either CEP or CET inhibits counting.
The AC/ACT163 uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
the Up mode, or min to max in the Down mode, to start its
final cycle. Since this final cycle takes 16 clocks to com-
plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
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74163 Даташит, Описание, Даташиты
State Diagram
Block Diagram
FIGURE 1.
FIGURE 2.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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