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PDF S3843P Data sheet ( Hoja de datos )
| Número de pieza | S3843P | |
| Descripción | Current Mode PWM Controller | |
| Fabricantes | AUK corp | |
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Semiconductor
S3843P
Current Mode PWM Controller
Descriptions
The S3843 is fixed Current PWM controller for Off-line and DC-DC converter applications.
The internal circuits feature a trimmed oscillator for precise duty cycle control, a
temperature compensated reference, high gain error amplifier current sensing comparator,
and a high current totempole output for driving a power MOSFET. Protection circuitly
includes built in under voltage lockout and current limiting. S3843 have UVLO threshold of
8.4V(on) and 7.6V(off). S3843 can operate within 100% duty cycle.
Features
• Optimized for off-line and DC to DC converters
• Low start up current < 1 mA
• Operating range up to 500 KHz
• Pulse-by-pulse current limiting
• Under Voltage Lock Out with hysteresis
• High current totempole output
• Short shutdown delay time ; typical 100nsec
Ordering Information
Type NO.
Marking
Package Code
S3843P
S3843P
DIP-8
Outline Dimensions
unit : mm
PIN Connections
1. Output / Compensation
2. Voltage feedback. Input
3. Current sense Input
4. Rt/Ct
5. GND
6. Output
7. Vcc
8. Vref
KSI-L007-000
1
1 page  
S3843P
4. Current Sense Circuit
Iβ
Ipeak =
R(V pin 1 - 2V be )
3R x Rs
R
C
Rs
ER R O R
AMP
2R
R IV
1
COMP
3
CUR R ENT
S ENS E
CUR R ENT
S ENS E
CO MP A R A T O R
G ND
5
A normal operating conditions occurs when the power supply output is overloaded or if output voltage to 1.0V
Therefore the maximum peak switch current is lpk(max)=1.0V/Rs, and under the normal operating conditions the
peak inductor current controlled by the voltage at pin1.
5. Shutdown Techniques
4.7K
8 V REF
1 COMP
Shutdown of the S3843 can be
4.7K
5.00
3 ISENSE
accomplished by two methods;
either raise pin3 above 1V or pull
S HUT
DO W N
T O CUR R ENT
S ENS E R ES IS T O R
S HUT
DOW N
pin1 below a voltage two diodes
drops above ground. Either causes
the output of the PWM method
comparator to be high (refer to
block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after
the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be
accomplished by adding an SCR which turn off, allowing the SCR to reset.
KSI-L007-000
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet S3843P.PDF ] | |
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