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PDF S3C2500B Data sheet ( Hoja de datos )

Número de pieza S3C2500B
Descripción 32-Bit RISC Microprocessor
Fabricantes Samsung semiconductor　
Logotipo Samsung semiconductor Logotipo



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21-S3C2500B-032003
USER'S MANUAL
S3C2500B
32-Bit RISC
Microprocessor
Revision 1

1 page




S3C2500B pdf
Table of Contents (Continued)
Chapter 3
Instruction Set
3.1 Instruction Set Summay .................................................................................................................... 3-1
3.1.1 Format Summary................................................................................................................... 3-1
3.1.2 Instruction Summary.............................................................................................................. 3-2
3.2 The Condition Field........................................................................................................................... 3-4
3.3 Branch and Exchange (BX) ............................................................................................................... 3-5
3.3.1 Instruction Cycle Times.......................................................................................................... 3-5
3.3.2 Assembler Syntax.................................................................................................................. 3-5
3.3.3 Using R15 as an Operand...................................................................................................... 3-5
3.4 Branch and Branch with Link (B, BL) ................................................................................................. 3-7
3.4.1 The Link Bit ........................................................................................................................... 3-7
3.4.2 Instruction Cycle Times.......................................................................................................... 3-7
3.4.3 Assembler Syntax.................................................................................................................. 3-8
3.5 Data Processing................................................................................................................................ 3-9
3.5.1 CPSR Flags........................................................................................................................... 3-11
3.5.2 Shifts ..................................................................................................................................... 3-12
3.5.3 Immediate Operand Rotates .................................................................................................. 3-16
3.5.4 Writing to R15........................................................................................................................ 3-16
3.5.5 Using R15 as an Operand...................................................................................................... 3-16
3.5.6 Teq, Tst, Cmp and CMN Opcodes ......................................................................................... 3-16
3.5.7 Instruction Cycle Times.......................................................................................................... 3-17
3.6.8 Assembler Syntax.................................................................................................................. 3-17
3.6 PSR Transfer (MRS, MSR) ............................................................................................................... 3-19
3.6.1 Operand Restrictions ............................................................................................................. 3-19
3.6.2 Reserved Bits ........................................................................................................................ 3-21
3.6.3 Instruction Cycle Times.......................................................................................................... 3-21
3.6.4 Assembler Syntax.................................................................................................................. 3-22
3.7 Multiply and Multiply-Accumulate (MUL, MLA) .................................................................................. 3-23
3.7.1 CPSR Flags........................................................................................................................... 3-24
3.7.2 Instruction Cycle Times.......................................................................................................... 3-24
3.7.3 Assembler Syntax.................................................................................................................. 3-24
3.8 Multiply Long and Multiply-Accumulate Long (MULL, MLAL) ............................................................. 3-25
3.8.1 Operand Restrictions ............................................................................................................. 3-25
3.8.2 CPSR Flags........................................................................................................................... 3-26
3.8.3 Instruction Cycle Times.......................................................................................................... 3-26
3.8.4 Assembler Syntax.................................................................................................................. 3-27
3.9 Single Data Transfer (LDR, STR)...................................................................................................... 3-28
3.9.1 Offsets and Auto-Indexing ..................................................................................................... 3-29
3.9.2 Shifted Register Offset........................................................................................................... 3-29
3.9.3 Bytes and Words ................................................................................................................... 3-29
3.9.4 Use of R15............................................................................................................................. 3-31
3.9.5 Restriction on the Use of Base Register ................................................................................. 3-31
3.9.6 Data Aborts............................................................................................................................ 3-31
3.9.7 Instruction Cycle Times.......................................................................................................... 3-31
3.9.8 Assembler Syntax.................................................................................................................. 3-32
iv S3C2500B RISC MICROCONTROLLER

5 Page





S3C2500B arduino
Table of Contents (Continued)
Chapter 8
HDLC Controller
8.1 Overview .......................................................................................................................................... 8-1
8.2 Features............................................................................................................................................ 8-2
8.3 Function Descriptions........................................................................................................................ 8-3
8.3.1 HDLC Frame Format ............................................................................................................. 8-4
8.4 Protocol Features.............................................................................................................................. 8-6
8.4.1 Invalid Frame ........................................................................................................................ 8-6
8.4.2 Zero Insertion and Zero Deletion............................................................................................ 8-6
8.4.3 Abort...................................................................................................................................... 8-6
8.4.4 Idle and Time Fill ................................................................................................................... 8-6
8.4.5 FIFO Structure....................................................................................................................... 8-7
8.4.6 Two-Channel DMA Engine..................................................................................................... 8-7
8.4.7 Baud Rate Generator............................................................................................................. 8-7
8.4.8 Digital Phase-Locked Loop (DPLL) ........................................................................................ 8-9
8.4.9 Clock Usage Method.............................................................................................................. 8-9
8.5 HDLC Operational Description .......................................................................................................... 8-11
8.5.1 HDLC Initialization ................................................................................................................. 8-11
8.5.2 HDLC Data Encoding/Decoding ............................................................................................. 8-12
8.5.3 HDLC Data Setup and Hold Timing with Clock....................................................................... 8-13
8.5.4 HDLC Transmitter Operation ................................................................................................. 8-14
8.5.5 HDLC Receiver Operation ..................................................................................................... 8-16
8.5.6 Hardware Flow Control .......................................................................................................... 8-17
8.5.7 Memory Data Structure.......................................................................................................... 8-19
8.5.8 Data Buffer Descriptor ........................................................................................................... 8-20
8.6 Buffer Descriptor............................................................................................................................... 8-21
8.6.1 Transmit Buffer Descriptor ..................................................................................................... 8-21
8.6.2 Receive Buffer Descriptor...................................................................................................... 8-22
8.7 HDLC Special Registers.................................................................................................................... 8-24
8.7.1 HDLC Global Mode Register.................................................................................................. 8-27
8.7.2 HDLC Control Register .......................................................................................................... 8-30
8.7.3 HDLC Status Register ........................................................................................................... 8-36
8.7.4 Summary............................................................................................................................... 8-36
8.7.5 HDLC Interrupt Enable Register............................................................................................. 8-42
8.7.6 HDLC Tx Fifo......................................................................................................................... 8-44
8.7.7 HDLC Rx Fifo ........................................................................................................................ 8-45
8.7.8 HDLC Brg Time Constant Registers....................................................................................... 8-46
8.7.9 HDLC Preamble Constant Register........................................................................................ 8-47
8.7.10 HDLC Station Address Registers and Hmask Register ......................................................... 8-48
8.7.11 Dma Tx Buffer Descriptor Pointer Register .......................................................................... 8-49
8.7.12 Dma Rx Buffer Descriptor Pointer Register .......................................................................... 8-50
8.7.13 Maximum Frame Length Register ........................................................................................ 8-50
8.7.14 Receive Buffer Size Register ............................................................................................... 8-51
8.7.15 Synchronization Register ..................................................................................................... 8-51
8.7.16 Transparent Control Register ............................................................................................... 8-52
8.7.17 Tx Buffer Descriptor Count Register..................................................................................... 8-53
8.7.18 Rx Buffer Descriptor Count Register .................................................................................... 8-53
8.7.19 Tx Buffer Descriptor Maximum Count Register .................................................................... 8-54
8.7.20 Rx Buffer Descriptor Maximum Count Register.................................................................... 8-54
x S3C2500B RISC MICROCONTROLLER

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