S3C4530A PDF даташит
Спецификация S3C4530A изготовлена «Samsung semiconductor» и имеет функцию, называемую «16/32-bit RISC microcontroller is a cost-effective/ high-performance microcontroller». |
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Детали детали
Номер произв | S3C4530A |
Описание | 16/32-bit RISC microcontroller is a cost-effective/ high-performance microcontroller |
Производители | Samsung semiconductor |
логотип |
30 Pages
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S3C4530A
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
INTRODUCTION
Samsung's S3C4530A 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4530A, is designed for use in
managed communication hubs and routers.
The S3C4530A is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.
The S3C4530A offers a configurable 8-Kbyte unified cache/SRAM and Ethernet controller which reduces total
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the
S3C4530A has been fully verified in Samsung's state-of-the-art ASIC test environment.
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels with full
modem interface signal and 32byte buffer, 2-channel GDMA, two 32-bit timers, and 26 programmable I/O ports.
On-board logic includes an interrupt controller, DRAM/ SDRAM controller, and a controller for ROM/SRAM and
flash memory. The System Manager includes an internal 32-bit system bus arbiter and an external memory
controller.
The following integrated on-chip functions are described in detail in this user's manual:
— 8-Kbyte unified cache/SRAM
— I2C interface
— Ethernet controller
— HDLC controller
— GDMA
— UART
— Timers
— Programmable I/O ports
— Interrupt controller
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PRODUCT OVERVIEW
FEATURES
Architecture
• Integrated system for embedded ethernet
applications
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported basically, the
internal architecture is big-endian.
So, the little-endian mode only support for
external memory.
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
• Boundary scan
System Manager
• 8/16/32-bit external bus support for
ROM/SRAM, flash memory, DRAM, and
external I/O
• One external bus master with bus request/
acknowledge pins
• Support for EDO/normal or SDRAM
• Programmable access cycle (0-7 wait cycles)
• Four-word depth write buffer
• Cost-effective memory-to-peripheral DMA
interface
Unified Instruction/Data Cache
• Two-way, set-associative, unified 8-Kbyte cache
• Support for LRU (least recently used) protocol
• Cache is configurable as an internal SRAM
I2C Serial Interface
• Master mode operation only
• Baud rate generator for serial clock generation
Ethernet Controller
• DMA engine with burst mode
• DMA Tx/Rx buffers (256 bytes Tx, 256 bytes
Rx)
• MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes
Rx)
S3C4530A
• Data alignment logic
• Endian translation
• 100/10-Mbit per second operation
• Full compliance with IEEE standard 802.3
• MII(10/100Mbps) or 7-wire 10-Mbps interface
• Station management signaling
• On-chip CAM (up to 21 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD generation
HDLCs
• HDLC protocol features:
— Flag detection and synchronization
— Zero insertion and deletion
— Idle detection and transmission
— FCS generation and detection (16-bit)
— Abort detection and transmission
• Address search mode (expandable to 4 bytes)
• Selectable CRC or No CRC mode
• Automatic CRC generator preset
• Digital PLL block for clock recovery
• Baud rate generator
• NRZ/NRZI/FM/Manchester data formats for
Tx/Rx
• Loop-back and auto-echo modes
• Tx/Rx FIFOs have 8-word (8 × 32-bit) depth
• Selectable 1-word or 4-word data transfer mode
• Data alignment logic
• Endian translation
• Programmable interrupts
• Modem interface
• Up to 10 Mbps operation
• HDLC frame length based on octets
• 2-channel DMA buffer descriptor for Tx/Rx on
each HDLC
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S3C4530A
DMA Controller
• 2-channel General DMA for memory-to-
memory, memory-to-UART, UART-to-memory
data transfers without CPU intervention
• Initiated by a software or external DMA request
• Increments or decrements a source or
destination address in 8-bit, 16-bit or 32-bit data
transfers
• 4-data burst mode
UARTs
• Two UART (serial I/O) blocks with DMA-based
or interrupt-based operation
• High speed(460Kbps) UART support with 32
byte Tx/Rx FIFO and modem interface signals
• Support for 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit and receive
• Automatic baud rate detection
• Eight control character comparison for software
control
• Programmable baud rates
• 1 or 2 stop bits
• Odd or even parity
• Break generation and detection
• Parity, overrun, and framing error detection
• ×16 clock mode
• Infra-red (IR) Tx/Rx support (IrDA)
Timers
• Two programmable 32-bit timers
• Interval mode or toggle mode operation
PRODUCT OVERVIEW
Programmable I/O
• 26 programmable I/O ports
• Pins individually configurable to input, output, or
I/O mode for dedicated signals
Interrupt Controller
• 21 interrupt sources, including 4 external
interrupt sources
• Normal or fast interrupt mode (IRQ, FIQ)
• Prioritized interrupt handling
PLL
• The external clock can be multiplied by on-chip
PLL to provide high frequency system clock
• The input frequency range is 10-40 MHz
• The output frequency is 5 times of input clock.
To get 50 MHz, input clock frequency should be
10 MHz.
Operating Voltage Range
• 3.3 V ± 5 %
Operating Temperature Range
oo
• 0 C to + 70 C
Operating Frequency
• Up to 50 MHz
Package Type
• 208 pin QFP
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Номер в каталоге | Описание | Производители |
S3C4530A | 16/32-bit RISC microcontroller is a cost-effective/ high-performance microcontroller | Samsung semiconductor |
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