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PDF S3C7281 Data sheet ( Hoja de datos )
| Número de pieza | S3C7281 | |
| Descripción | The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core CPU and contains ROM/ RAM. | |
| Fabricantes | Samsung semiconductor | |
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S3C7281
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
OVERVIEW
The S3C7281 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It is built around the SAM48 core
CPU and contains ROM, RAM. 14 I/O lines, buzzer and inverted buzzer output, and LCD driver/controller with an
up-to-64-dot.
The S3C7281 can be used for dedicated control functions in a variety of applications, and is especially designed
for LCD general purpose.
1-1
1 page  
S3C7281
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Pin Name
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P2.0 - P2.7
CLO
BUZ
BUZ
KS0
KS1
SEG0
SEG1
SEG2-SEG9
SEG10-SEG17
COM0
COM1
COM2
COM3
XTIN
XTOUT
VDD
VSS
RESET
TEST
Table 1-1. S3C7281 Pin Descriptions
Pin Type
Description
I/O 4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
1-bit unit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. Individual pins can be allocated as input or
output(1-bit unit). The n-channel open-drain or push-
pull output can be selected by software(1-bit unit).
I/O 4-bit I/O port.
1-bit or 4-bit write and test is possible.
4-bit unit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. The pins can be allocated as input or output(4-bit
unit). The n-channel open-drain or push-pull output
can be selected by software(4-bit unit).
O 8-bit output port.
1-bit, 4-bit, 8-bit read/write and test is possible.
The n-channel open-drain or push-pull output can be
selected by software(4-bit unit).
I/O Clock output.
I/O Buzzer signal output.
I/O Inverted buzzer signal output.
I/O External interrupt with falling edge detection.
O LCD segment signal output.
O LCD segment signal output.
O LCD segment signal output.
O LCD common signal output.
O LCD common signal output.
– Crystal oscillator pins for subsystem clock.
Number
31
30
29
28
5
6
27 - 20
31
30
29
5
6
10
11
12 - 19
20 - 27
8
9
10
11
2
3
Share Pin
CLO
BUZ
BUZ
KS0
KS1
SEG17-
SEG10
P0.0
P0.1
P0.2
P1.0
P1.1
COM0
COM1
–
P2.7 - P2.0
–
SEG0
SEG1
–
– Main power supply.
32 –
– Ground.
1–
I Chip reset signal input.
7–
I Chip test signal input (must be connected to VSS). 4 –
1-5
5 Page 
S3C7281
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Input High Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XTIN
Input Low Leakage
Current
ILIL1 VI = 0 V
All input pins except RESET
and XTIN
ILIL2
VI = 0 V
XTIN
Output High Leakage
Current
ILOH
VO = VDD
All output pins
Output Low Leakage
Current
ILOL VO = 0 V
All output pins
Pull-Up Resistor
RL1 VI = 0 V; VDD = 5V
Ports 0, 1
VDD = 3V
RL2 VI = 0 V; VDD = 5V; RESET
VDD = 3V
LCD Voltage Dividing
Resistor
RLCD TA = + 25 °C
VLC0-COMi
Voltage Drop (i = 0-3)
VDC – 15 uA per common pin
VLC0-SEGx Voltage
Drop (x = 0–17)
VDS – 15 uA per common pin
Middle Output
VLC0 VDD = 1.8V to 5.5V, 1/3 bias
Voltage (note)
VLC1 LCD clock = 0Hz
VLC2
Min Typ Max Units
– – 3 µA
20
– – –3
– 20
––3
– – –3
25 50 75 kΩ
50 100 150
100 200 300
250 500 750
120 170 220
– – 120 mV
– – 120
VDD-0.2
2VDD/3-0.2
VDD/3-0.2
VDD
2VDD/3
VDD/3
VDD+0.2
2VDD/3+0.2
VDD/3+0.2
V
NOTE: It is middle output voltage when 1/4 duty and 1/3 bias.
13-3
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet S3C7281.PDF ] | |
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