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PDF S3C72K8 Data sheet ( Hoja de datos )
| Número de pieza | S3C72K8 | |
| Descripción | singl-chip CMOS microcontroller | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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S3C72K8/P72K8
1 PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to-
320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an
excellent design solution for a wide variety of applications which require LCD functions.
Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8.
S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM.
The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration.
1-1
1 page  
S3C72K8/P72K8
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72K8 Pin Descriptions
Pin Name Pin
Type
Description
P0.0
P0.1
P0.2
P0.3
I/O 4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I 4-bit input port.
1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.
An interrupt is generated by digital input at P1.0,
P1.1.
P2.0–P2.3 I/O Same as port 0 except that 8-bit read/write and test is
possible.
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
I/O Same as port 0 except that port 4 is 3-bit I/O port.
P5.0–P5.7 O Output port for 1-bit data
Circuit
Type
E–2
F–4
F–4
A–3
A–3
E–2
E–2
H–11
SCK
SO
SI
BUZ
K0–K3
INT0
INT1
INT2
INT4
I/O Serial I/O interface clock signal
I/O Serial data output
I/O Serial data input
I/O 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at
the watch timer clock frequency of 32.768 kHz.
I/O External interrupt. The triggering edge is selectable.
I External interrupts. The triggering edge for INT0 and
INT1 is selectable.
I Quasi-interrupt with detection of rising or falling
edges
I External interrupts with detection of rising and falling
edges
E–2
E–2
E–2
E–2
E–2
F–4
A–3
A–3
Pin
Number
8
9
10
11
Share Pin
K0/SCK
K1/SO
K2/SI
K3/BUZ
20 INT0/CIN0
21 INT1/CIN1
22 INT2
23 INT4
24–27
–
28
29
30
31
32
33
34
75–
80,1,2
8
9
10
11
–
–
LCDSY
LCDCK
CLO
TCL0
TCLO0
SEG32–
SEG39
P0.0/K0
P0.1/K1
P0.2/K2
P0.3/K3
8–11
20
21
22
P0.0–P0.3
P1.0/CIN0
P1.1/CIN1
P1.2
23 P1.3
1-5
5 Page 
S3C72K8/P72K8
15 ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72K8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Comparator electrical characteristics
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement points
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET signal
— Input timing for external interrupts
— Serial data transfer timing
15-1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3C72K8.PDF ] | |
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