|
|
PDF S3C7515 Data sheet ( Hoja de datos )
| Número de pieza | S3C7515 | |
| Descripción | The S3C7515/P7515 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core/ SAM47 | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de S3C7515 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
S3C7515/P7515
OVERVIEW
The S3C7515/P7515 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P7515 is a
microcontroller which has 16-kbyte one-time-programmable EPROM but its functions are same to S3C7515.
With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the S3C7515/P7515 offers
an excellent design solution for a wide variety of telecommunication applications.
Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C7515/P7515's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.
DEVELOPMENT SUPPORT0
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-
ment environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS tool set includes versatile debugging, trace, instruction
timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been
designed specifically for the SMDS environment and accepts assembly language sources in a variety of
microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for
SMDS compatibility.
S MSUNG
1–2
ELECTRONICS
1 page  
PRODUCT OVERVIEW
S3C7515/P7515
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C SC2 SC1 SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated
clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce three CPU clock frequencies — fxx/4, fxx/8, or fxx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
or 3.91 milliseconds at the watch timer clock frequency of 32.768 kHz. The following components support
interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-6
5 Page 
PRODUCT OVERVIEW
S3C7515/P7515
Table 1-1. S3C7515/P7515 Pin Descriptions (Continued)
Pin Name
P10.0–P10.3
P11.0–P11.3
P12.0–P12.3
P13.0–P13.2
DTMF
SCK
SO
SI
BTCO
INT0, INT1
INT2
INT4
TCLO0
TCLO1
CLO
BUZ
TCL0
TCL1
KS0–KS3
KS4–KS7
Pin Type
I/O
Description
Same as port 9.
Ports 10 and 11 can be paired to support 8-bit data
transfer.
I/O 4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-down resistors are software assignable;
pull-down resistors are automatically disabled for
output pins.
I/O 3-bit I/O port; characteristics are same as port 9.
O DTMF output.
I/O Serial I/O interface clock signal
I/O Serial data output
I/O Serial data input
I/O Basic timer clock output
I External interrupts. The triggering edge for INT0 and
INT1 is selectable. INT0 is synchronized to system
clock.
I Quasi-interrupt with detection of rising edges
I External interrupt with detection of rising and falling
edges.
I/O Timer/counter 0 clock output
I/O Timer/counter 1 clock output
I/O Clock output
I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
the watch timer clock frequency of 32.768 kHz for
buzzer sound
I/O External clock input for timer/counter 0
I/O External clock input for timer/counter 1
I/O Quasi-interrupt inputs with falling edge detection
Number
19–16
(12–9)
23–20
(16–13)
27–24
(20–17)
7–5
(64–62)
31 (24)
15 (8)
14 (7)
13 (6)
12 (5)
4, 3
(61, 60)
2 (59)
1 (58)
11 (4)
10 (3)
9 (2)
8 (1)
34 (27)
33 (26)
51–48
(44–41)
55–52
(48–45)
* Parentheses indicate pin number for 64 QFP package.
Share Pin
–
–
–
–
P0.0
P0.1
P0.2
P0.3
P1.0, P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P6.0–P6.3
P7.0–P7.3
1-12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S3C7515.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| S3C7515 | The S3C7515/P7515 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core/ SAM47 | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |