PDF S5L9284D01-Q0R0 Data sheet ( Hoja de datos )

Número de pieza	S5L9284D01-Q0R0
Descripción	DIGITAL SIGNAL PROCESSOR
Fabricantes	Samsung semiconductor
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No Preview Available ! DIGITAL SIGNAL PROCESSOR INTRODUCTION The S5L9284D is a CMOS integrated circuit designed for the digital audio signal processor. It is a monolithic IC with built-in 16K SRAM and DPLL. It is similar to S5L9283 IC but has advanced error correction ability. 80−QFP−1420C FEATURES • EFM data demodulation • Built-in frame sync detection, protection and insertion circuit • C1: 2 error correction; C2: 4 erasure correction • Interpolation • Subcode data serial output • CLV servo controller • Tracking counter • MICOM interface • Built-in 16K SRAM • Digital audio output (TX) • Built-in digital PLL and analog PLL • Double speed function • Single power supply: +5V ORDERING INFORMATION Device S5L9284D01-Q0R0 Package 80-QFP-1420C Operating Temperature −20°C to +75°C S5L9284D 1 1 page DIGITAL SIGNAL PROCESSOR S5L9284D PIN DESCRIPTION (Continued) Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Symbol SBCK SBDT DVDD1 MUTE MLT MDAT MCK DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 52 /PBCK 53 DVSS2 54 FSDW 55 ULKFS 56 /JIT 57 C4M 58 C16M 59 /WE 60 / CS 61 SEL1 62 SEL2 I/O Description I Subcode data bit clock O Subcode serial data output − Digital supply voltage 1 I Mute control input (“H”: Mute ON) I Latch signal input from micom I Serial data input from micom I Serial data transferring clock input from micom I/O Data port 7 for external SRAM (MSB) I/O Data port 6 for external SRAM I/O Data port 5 for external SRAM I/O Data port 4 for external SRAM I/O Data port 3 for external SRAM I/O Data port 2 for external SRAM I/O Data port 1 for external SRAM I/O Data port 0 for external SRAM (LSB) I/O Monitoring output for C1 error correction (RA0) I/O Monitoring output for C1 error correction (RA1) I/O Monitoring output for C2 error correction (RA2) I/O Monitoring output for C2 error correction (RA3) I/O C2 decoder flag (“H”: when the processing C2 code is in impossible correction status /RA4) I/O VCOI/2 clock (4.3218/8.6436 MHz), when locked in with EFMI (RA5) − Digital ground 2 I/O Unprotected frame sync (RA6) I/O Frame sync protection status (RA7) I/O RAM overflow and underflow status (RA8) I/O 4.2336 MHz clock output (RA9) I/O 16.9344 MHz clock output (RA10) I/O Write enable output to external SRAM I/O Chip select output to external SRAM I X-tal selection terminal (“L”:16.9344 MHz, “H”: 33.8688 MHz) I DPLL selection terminal (“L”: DPLL, “H”: APLL) 5 5 Page DIGITAL SIGNAL PROCESSOR S5L9284D CNTL-Z Register It is a register to control the zero cross mute of audio data, the phase terminal control, the phase servo and having CRCF data in SQDT or not. ZCMT HIPD NCLV CRCQ DATA D3 D2 D1 D0 DATA = 0 Zero cross mute is OFF It operates phase normally Phase servo is acted by frame sync SQDT output except for SQOK DATA = 1 Zero cross mute is ON The phase becomes “L” to “Hi-Z” Phase servo is controlled by base counter SQDT = CRCF when S0S1 = “H” CNTL-S Register It is a register to control frame sync protection and attenuation. FSEM 0 0 1 1 FSEL 0 1 0 1 FRAME 2 4 8 13 WSEL 0 1 CLOCK ±3 ±7 ATTM 0 0 1 1 MUTE 0 1 0 1 dB 0 −∞ − 12 − 12 CNTL-L, U Register After the number of tracks that must be counted is input from micom , the data is loaded to the tracking counter by the CNTL-L, U register. CNTL-W Register It is a register to control CLV-servo. DATA DATA = 0 DATA = 1 COM D3 XTFR/4 and PBFR/4 WB D2 XTFR/32 XTFR/16 WP D1 XTFR/4 XTFR/2 GAIN D0 −12dB 0dB Comment Phase comparison frequency control during Phase - mode Bottom hold period control during speed or HSpeed-mode Peak hold period control during Speed-mode SMDP gain control during Speed or HSpeed-Mode 11 11 Page

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