S5T8554B01 Datasheet PDF - Samsung semiconductor
| Part Number | S5T8554B01 | |
| Description | 1 CHIP CODEC | |
| Manufacturers | Samsung semiconductor | |
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There is a preview and S5T8554B01 download ( pdf file ) link at the bottom of this page. Total 14 Pages | ||
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1 CHIP CODEC
INTRODUCTION
The S5T8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide all the
functions required to interface a full-duplex voice telephone circuit
with a time-division-multiplex (TDM) system.
These devices are designed to perform the transmit encoding and
receive decoding as well as the transmit and receive filtering
functions in PCM system. They are intended to be used at the
analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices
perform the encoding and decoding of voice and call progress tones
as well as the signalling and supervision information.
16-CERDIP
16-DIP-300A
8−DIP−300
FEATURES
• Complete CODEC and filtering system
• Meets or exceeds AT&T D3/D4 and CCITT specifications
µ-Law: S5T8554B, A-Law: S5T8557B
• On-chip auto zero, sample and hold, and precision voltage references
• Low power dissipation: 60mW (operating), 3mW (standby)
• ± 5V operation
• TTL or CMOS compatible
• Automatic power down
ORDERING INFORMATION
Device
S5T8554B02-L0B0
S5T8557B02-L0B0
S5T8554B01-D0B0
S5T8557B01-D0B0
S5T8554B01-S0B0
S5T8557B01-S0B0
Package
16-CERDIP
16-DIP-300A
16-SOP-BD300
Operating Temperature
−25°C to 125°C
−25°C to +70°C
−25°C to +70°C
S5T8554B/7B
1
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1 CHIP CODEC
S5T8554B/7B
TIMING CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;
typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)
Characteristic
Frequency of Master Clock
Rise Time of Bit Clock
Fall Time of Bit Clock
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLKX High
to Data Valid
Delay Time to TSX Low
Delay Time from BCLKX Low to
Data Output Disabled
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
Set-Up Time from DR Valid to
BCLKR/X Low
Hold Time from FSR/X Low to
DR Invalid
Set-Up Time from FSR/X to
BCLKR/X Low
Width of Master Clock High
Width of Master Clock Low
Rise Time of Master Clock
Fall Time of Master Clock
Set-Up Time from BCLKX High
(and FSX In Long Frame Sync
Mode) to MCLKX Falling Edge
Symbol
fMCK
tR (BCK)
tF (BCK)
tH (LFS)
Test Conditions
Depends on the device used
and the BCLKR/CLKSEL Pin.
MCLKX and MCLKR
tPB = 488ns
tPB = 488ns
Long frame only
tH (RFS) Short frame only
tSU (FBCL) Long frame only
tD (HDV)
tD (TSXL)
tD (LDD)
Load = 150pF plse 2 LSTTL
loads
Load = 150pF plse 2 LSTTL
loads
−
tD (VD) CL = 0pF to 150pF
tSU (DRBL)
−
tH (BLDR)
−
tSU (FBLS) Short frame sync pulse (1 or 2
bit clock periods long) (Note 1)
tW (MCKH)
tW (MCKL)
tR (MCK)
tF (MCK)
tSU (BHMF)
MCLKX and MCLKR
MCLKX and MCLKR
MCLKX and MCLKR
MCLKX and MCLKR
First bit clock after the leading
edge FSX
Min.
−
−
−
0
Typ.
1.536
1.544
2.048
−
−
−
Max.
−
50
50
−
0−−
80 −
−
0 − 180
− − 140
50 − 165
20 − 165
50 −
50 −
50 −
160 −
160 −
−−
−−
−−
−
−
−
−
−
50
50
−
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
−
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for S5T8554B01 electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ S5T8554B01.PDF Datasheet ] | |
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