S5T8554B03-D0B0 Datasheet PDF - Samsung semiconductor
| Part Number | S5T8554B03-D0B0 | |
| Description | CODEC FOR DIGITAL ANSWERING PHONE | |
| Manufacturers | Samsung semiconductor | |
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CODEC FOR DIGITAL ANSWERING PHONE
S5T8554B03
INTRODUCTION
The S5T8554B03 consists of on-chip PCM encoders, decoders (PCM CODECs)
and PCM line filter. This device provides all the functions required to
interface a full-duplex voice telephone circuit, digital answering phone. This
device is designed to perform the transmit encoding and receive decoding as
well as the transmit and receive filtering function in PCM system. Also it is inten-
ded to be used at the analog termination of a PCM line / trunk. This device
provide the Band pass filtering of the analog signals prior to encoding and
after decoding. This combination device performs the encoding and decoding
of voice and call progress tones as well as the signaling and supervision
information.
16−DIP−300
16−SOP−BD300
FEATURES
• Complete CODEC and filtering system
• Encoding / Decoding : 8 bits µ-law PCM
• On-chip auto zero, sample and hold,
and precision voltage references
• Low power dissipation : 60mW ( operating )
3mW ( standby )
• ± 5V operation
• TTL or CMOS compatible
• Automatic power down
ORDERING INFORMATION
Device
S5T8554B03-D0B0
S5T8554B03-S0B0
Package
16−DIP−300
16−SOP−BD300
Operating Temperature
0 ~ + 70°C
PIN CONFIGURATION
VBB 1
16 VFIXI+
GNDA 2
15 VFXI-
VFRO 3
14 GSX
VCC 4 S5KTS8585642B003 13 TSX
FSR 5
12 FSX
DR 6
11 DX
BCLKR/CLKSEL 7
10 BCLKX
MCLKR/PDN 8
9 MCLKX
1
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CODEC FOR DIGITAL ANSWERING PHONE
S5T8554B03
TIMING CHARACTERISTICS
(Unless otherwise specified : Ta = 0°C to 70°C, Vcc = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V )
Characteristic
Frequency of Master Clock
System
Test Conditions
fMCK Depends on the device used and
the BCLKR /CLKSEL pin. MCLKx
and MCLK
Rise time of Bit Clock
tR(BCK)
tPB = 488ns
Fall Time of Bit Clock
tF(BCK)
tPB = 488ns
Hold Time for Bit Clock low to tH(LFS)
Frame sync
Long Frame only
Hold Time for Bit Clock High to tH(HFS)
Frame sync
Short Frame only
Set-up Time from Frame sync tSU(FBCL) Long Frame only
to Bit Clock low
Delay time from BCLKx High tD(HDV)
to data valid
Load = 150pF + 2 LSTTL loads
Delay time to /TSx low
tD(/TSXL) Load = 150pF + 2 LSTTL loads
Delay time from BCLKx low to tD(LDD)
data output disable
Delay Time to valid data from tD(VD)
FSx or BCLKx
CL = 0 pF to 150 pF
Whichever comes later.
Set-up Time from DR valid to
BCLK x/R low
tSU(DRBL)
−
Hold time from BCLK x/R low tH(BLDR)
to DR invalid
−
Set-up time from FS x/R to
BCLK x/R low
tSU(FBLS) Short Frame sync pulse (1 or 2 bit
clock periods long ) : note1
Width of master clock High
tW(MCKH) MCLKx and MCLKR
Width of master clock Low
tW(MCKL) MCLKx and MCLKR
Rise Time of Master clock
tR(MCK) MCLKx and MCLKR
Fall Time of Master clock
tF(MCK) MCLKx and MCLKR
Set-up time from BCLKx High
(FSx in Long Frame Sync
mode ) to MCLKx falling edge
tSU(BHMF) 1’s t bit clock after the leading
edge of FSx
Period of Bit Clock
tCK
−
Width of Bit clock High
tW(BCKH) VIH = 2.2V
Width of Bit clock Low
tW(BCKL) VIL = 0.6V
Hold time from BCLK x/R to
FS x/R low
tH(BLFL)
Short Frame sync pulse (1 or 2 bit
clock periods long ) : note1
Min.
−
−
−
−
−
0
Typ.
1.536
1.544
2.048
−
−
−
Max.
−
−
−
50
50
−
Unit
MHz
nS
nS
nS
0−
− nS
80 −
− nS
0 − 180 nS
− − 140 nS
50 − 165 nS
20 − 165 nS
50 −
− nS
50 −
− nS
50 −
− nS
160 −
160 −
−−
−−
50 −
− nS
− nS
50 nS
50 nS
− nS
485 488 15.725 nS
160 −
− nS
160 −
− nS
100 −
− nS
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for S5T8554B03-D0B0 electronic component. |
| Information | Total 13 Pages | |
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