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PDF S6B0794 Data sheet ( Hoja de datos )
| Número de pieza | S6B0794 | |
| Descripción | 160 SEG / COM DRIVER FOR STN LCD | |
| Fabricantes | Samsung semiconductor | |
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S6B0794
160 SEG / COM DRIVER FOR STN LCD
July, 2000
Ver. 3.0
Prepared by: Gyeong-Nam, Kim
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
1 page  
S6B0794 SPEC. VER 3.0
BLOCK DIAGRAM
160 SEG / COM DRIVER FOR STN LCD
FR 182
DISPOFFB 179
EIO1 181
EIO2 169
LP 180
XCK 178
V OR V 12R V43R V 5L
190 189 188 164
Y1 Y2
12
Y 159 Y 160
159 160
LEVEL
SHIFTER
ACTIVE
CONTROL
CONTROL
LOGIC
160 BITS 4-LEVEL DRIVER
160
160 BITS LEVEL SHIFTER
160
160 BITS LINE LATCH/SHIFTER
REGISTER
16 16 16 16 16 16 16 16 16 16
8BITS*2
DATA
LATCH
187 V 5L
163 V 43L
162 V 12L
161 V OL
L/R 166
MD 183
S/C 168
8
SP CONVERSION & DATA CONTROL
(4 to 8 or 8to 8)
DATA LATCH CONTROL
170 171 172 173 174 175 176 177
D I0 D I1 D I2 D I3 DI4 DI5 DI6 DI7
167 165 186
VDD VSS VSS
Figure 1. Block Diagram
5
5 Page 
S6B0794 SPEC. VER 3.0
160 SEG / COM DRIVER FOR STN LCD
PIN FUNCTION
Segment Mode
Symbol
Function
VDD Logic system power supply pin connects to +2.4 to +5.5V
VSS Ground pin connects to 0 V
V0R, V0L
V12R , V12L
V43R , V43L
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS<V43<V12<V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y160, externally connect ViR and ViL(i=0, 12, 43)
Input pin for display data
. In 4-bit parallel input mode, input data into the 4 pins DI0 – DI3.
DI0 – DI7
Connect DI4 – DI7 to VSS or VDD.
. In 8-bit parallel input mode, input data into the 8 pins DI0 – DI7.
XCK
Clock input pin for taking display data
. Data is read on the falling edge of the clock pulse.
Latch pulse input pin for display data
LP
. Data is latched on the falling edge of the clock pulse.
Direction selection pin for reading display data
L/R . When set to VSS level “L”, data is read sequentially from Y160 to Y1.
. When set to VDD level H”, data is read sequentially from Y1 to Y160.
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins (Y1-Y160) are set to level
VSS.
DISPOFFB
. While set to “L”, the contents of the line latch are reset, but read the display
data in the data latch regardless of condition of DISPOFFB.
When the DISPOFFB function is canceled, the driver outputs deselect
level(V12 or V43), then outputs the contents of the data latch on the next
falling edge of the LP. That time, if DISPOFFB removal time can not keep
regulation what is shown AC characteristics (page 21), can not output the
reading data correctly.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S6B0794.PDF ] | |
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