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PDF SC1186CSW Data sheet ( Hoja de datos )

Número de pieza SC1186CSW
Descripción PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER/ DUAL LOW DROPOUT REGULATOR CONTROLLER
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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No Preview Available ! SC1186CSW Hoja de datos, Descripción, Manual

PRELIMINARY - December 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1186 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to
implement three DC/DC converters for powering
advanced microprocessors such as Pentium® II & III.
The SC1186 switching section features an integrated
5 bit D/A converter, latched drive output for
enhanced noise immunity, pulse by pulse current
limiting and logic compatible shutdown. The SC1186
switching section operates at a fixed frequency of
140kHz, providing an optimum compromise between
size, efficiency and cost in the intended application
areas. The integrated D/A converter provides
programmability of output voltage from 2.0V to 3.5V
in 100mV increments and 1.30V to 2.05V in 50mV
increments with no external components.
The SC1186 linear sections are low dropout regula-
tors with short circuit protection, supplying 1.5V for
GTL bus and 2.5V for non-GTL I/O. The Reference
voltage is made available for external linear
regulators.
FEATURES
Synchronous design, enables no heatsink solution
95% efficiency (switching section)
5 bit DAC for output programmability
Designed for Intel Pentium® ll & III requirements
1.5V, 2.5V short circuit protected linear controllers
1.265V ± 1.5% Reference available
APPLICATIONS
Pentium® ll & III microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
ORDERING INFORMATION
Part Number(1)
Package
Linear
Voltage
Temp.
Range (TJ)
SC1186CSW SO-24 1.5V/2.5V 0° to 125°C
Note:
(1) Add suffix ‘TR’ for tape and reel.
PIN CONFIGURATION
BLOCK DIAGRAM
Top View
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
4
5
6
7
8
9
10
11
12
24 GATE2
23 LDOV
22 VID0
21 VID1
20 VID2
19 VID3
18 VID4
17 VOSENSE
16 EN
15 BSTH
14 BSTL
13 DL
(24 Pin SOIC)
VID4
VID3
VID2
VID1
VID0
VOSENSE
AGND
LDOEN
LDOS1
GATE1
VCC
CS- CS+
REF
70mV
CURRENT
LIMIT
+
-
+
D/A -
-
ERROR
+
AMP
EN
OSCILLATOR
R
Q
S
2.5V FET
CONTROLLER
1.265V
REF
1.5V FET
CONTROLLER
LDOV REF
GATE2 LDOS2
LEVEL SHIFT AND
HIGH SIDE DRIVE
BSTH
DH
PGNDH
SHOOT-THRU
CONTROL
SYNCHRONOUS
MOSFET DRIVE
BSTL
DL
PGNDL
© 1999 SEMTECH CORP.
Pentium is a registered trademark of Intel Corporation
1
652 MITCHELL ROAD NEWBURY PARK CA 91320

1 page




SC1186CSW pdf
PRELIMINARY - December 2, 1999
APPLICATION CIRCUIT
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
© 1999 SEMTECH CORP.
5
652 MITCHELL ROAD NEWBURY PARK CA 91320

5 Page





SC1186CSW arduino
PRELIMINARY - December 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
Using 1.5X Room temp RDS(ON) to allow for temperature
rise.
FET type
IRL34025
IRL2203
RDS(on) (m) PD (W)
15 1.69
10.5 1.19
Package
D2PAK
D2PAK
Si4410 20
2.26 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into con-
duction at the beginning and end of the bottom switch
conduction period, so when the FET turns on and off,
there is very little voltage across it, resulting in low
switching losses. Conduction losses for the FET can be
determined by:
PCOND = I2O RDS(on) (1− δ)
For the example above:
FET type
IRL34025
IRL2203
Si4410
RDS(on) (m) PD (W)
15 1.33
10.5 0.93
20 1.77
Package
D2PAK
D2PAK
SO-8
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal
impedance is mostly determined by the heatsink used.
For the surface mount packages on double sided FR4, 2
oz printed circuit board material, thermal impedances of
40oC/W for the D2PAK and 80oC/W for the SO-8 are
readily achievable. The corresponding temperature rise
is detailed below:
Temperature rise (oC)
FET type Top FET Bottom FET
IRL34025 67.6
53.2
IRL2203 47.6
37.2
Si4410 180.8
141.6
INPUT CAPACITORS - since the RMS ripple current
in the input capacitors may be as high as 50% of the
output current, suitable capacitors must be chosen ac-
cordingly. Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on the linear controllers is
implemented by using the Rds(on) of the FETs. As
output current increases, the regulation loop maintains
the output voltage by turning the FET on more and
more. Eventually, as the Rds(on) limit is reached, the
FET will be unably to turn on more fully, and output
voltage will start to fall. When the output voltage falls
to approximately 50% of nominal, the LDO controller
is latched off, setting output voltage to 0. Power must
be cycled to reset the latch.
To prevent false latching due to capacitor inrush cur-
rents or low supply rails, the current limit latch is ini-
tially disabled. It is enabled at a preset time (nominally
2mS) after both the LDOV and LDOEN rails rise
above their lockout points.
To be most effective, the linear FET Rds(on) should
not be selected artificially low, the FET should be cho-
sen so that, at maximum required current, it is almost
fully turned on
If, for example, a linear supply of 1.5V at 4A is re-
quired from a 3.3V ± 5% rail, max allowable Rds(on)
would be.
Rds(on)max = (0.95*3.3-1.5)/4 400m
To allow for temperature effects 200mwould be a
suitable room temperature maximum, allowing a peak
short circuit current of approximately 15A for a short
time before shutdown.
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each po-
sition, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
© 1999 SEMTECH CORP.
11
652 MITCHELL ROAD NEWBURY PARK CA 91320

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