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PDF SC2200 Data sheet ( Hoja de datos )
| Número de pieza | SC2200 | |
| Descripción | Thin Client On a Chip | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 2002
Revision 3.0
Geode™ SC2200
Thin Client On a Chip
General Description
The Geode™ SC2200 Thin Client On a Chip device is a
member of the National Semiconductor® IA (Information
Appliance) on a Chip family of fully integrated x86 system
chips. The Geode SC2200 includes:
• The Geode GX1 processor module combines advanced
CPU performance with Intel MMX support, fully acceler-
ated 2D graphics, a 64-bit synchronous DRAM
(SDRAM) interface, a PCI bus controller, and a display
controller.
• A low-power CRT and TFT Video Processor module with
a Video Input Port (VIP), and a hardware video acceler-
ator for scaling, filtering, and color space conversion.
• The Core Logic module includes: PC/AT functionality, a
USB interface, an IDE interface, a PCI bus interface, an
LPC bus interface, Advanced Configuration Power Inter-
face (ACPI) version 1.0 compliant power management,
and an audio codec interface.
• The SuperI/O module has: three serial ports (UART1,
UART2, and UART3 with fast infrared), a parallel port,
two ACCESS.bus (ACB) interfaces, and a real-time
clock (RTC).
The block diagram shows the relationships between the
modules.
These features, combined with the device’s small form fac-
tor and low power consumption, make it ideal as the core
for a thin client application.
Block Diagram
GX1
CPU
Core
Memory Controller
2D Graphics
Accelerator
PCI Bus
Controller
Display
Controller
Fast-PCI Bus
Config.
Block
Video Processor
Video
Scaling
Video
Mixer
CRT I/F
TFT I/F
Video Input Port (VIP)
Host Interface
Clock & Reset Logic
IDE I/F
USB
PCI/Sub-ISA
Bus I/F
GPIO
Audio Codec I/F
LPC I/F
Bridge
X-Bus
Fast X-Bus
Core Logic
PIT
PIC
DMAC
Pwr Mgmnt
Configuration
ISA Bus I/F
RTC
SuperI/O
ISA Bus
I/F
Parallel
Port
ACB1
I/F
ACB2
I/F
UART1
UART2
UART3
& IR
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2002 National Semiconductor Corporation
www.national.com
1 page  
Table of Contents (Continued)
3.0 General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.1 CONFIGURATION BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.2 MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS . . . . . . . . 81
3.3 WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.3.1.1 WATCHDOG Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.3.2 WATCHDOG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3.2.1 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.4 HIGH-RESOLUTION TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.2 High-Resolution Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.2.1 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.5 CLOCK GENERATORS AND PLLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
27 MHz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
GX1 Module Core Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Internal Fast-PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SuperI/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Core Logic Module Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Video Processor Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.0 SuperI/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 MODULE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.3 CONFIGURATION STRUCTURE / ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.1
4.3.2
4.3.3
4.3.4
Index-Data Register Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Banked Logical Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Default Configuration Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.4 STANDARD CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.1 SIO Control and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.2 Logical Device Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.4.2.1
4.4.2.2
LDN 00h - Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LDN 01h - System Wakeup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.4.2.3
4.4.2.4
LDN 02h - Infrared Communication Port or Serial Port 3 . . . . . . . . . . . . . . . . . . 110
LDN 03h and 08h - Serial Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4.2.5
4.4.2.6
LDN 05h and 06h - ACCESS.bus Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . 112
LDN 07h - Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.5 REAL-TIME CLOCK (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.1
4.5.2
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RTC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.2.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.2.2 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5.2.3 Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5.2.4 Timekeeping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.5.2.5 Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.5.2.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.5.2.7 System Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.5.2.8 Oscillator Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.5.2.9 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.2.10 Battery-Backed RAMs and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Revision 3.0
5 www.national.com
5 Page 
Architecture Overview (Continued)
1.1 GX1 MODULE
The GX1 processor (silicon revision 8.1.1) is the central
module of the SC2200. For detailed information regarding
the GX1 module, refer to the Geode GX1 Processor Series
datasheet and the Geode GX1 Processor Series Silicon
Revision 8.1.1 errata.
The SC2200’s device ID is contained in the GX1 module.
Software can detect the revision by reading the DIR0 and
DIR1 Configuration registers (see Configuration registers
in the Geode GX1 Processor Series datasheet). The
SC2200 device errata contains the specific values.
1.1.1 Memory Controller
The GX1 module is connected to external SDRAM devices.
For more information see Section 2.4.2 "Memory Interface
Signals" on page 57, and the "Memory Controller" chapter
in the GX1 Processor Series datasheet.
There are some differences in the SC2200’s memory con-
troller and the stand-alone GX1 processor’s memory con-
troller:
1) There is drive strength/slew control in the SC2200 that
is not in the GX1. The bits that control this function are
in the MC_MEM_CNTRL1 and MC_MEM_CNTRL2
registers. In the GX1 processor, these bits are marked
as reserved.
2) The SC2200 supports two banks of memory. The GX1
supports four banks of memory. In addition, the
SC2200 supports a maximum of eight devices and the
GX1 supports up to 32 devices. With this difference,
the MC_BANK_CFG register is different.
Table 1-1 summarizes the 32-bit registers contained in the
SC2200’s memory controller. Table 1-2 gives detailed reg-
ister/bit formats.
GX_BASE+
Memory Offset
8400h-8403h
8404h-8407h
8408h-840Bh
840Ch-840Fh
8414h-8417h
8418h-841Bh
841Ch-841Fh
Table 1-1. SC2200 Memory Controller Register Summary
Width
(Bits) Type Name/Function
32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1
32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2
32 R/W MC_BANK_CFG. Memory Controller Bank Configuration
32 R/W MC_SYNC_TIM1. Memory Controller Synchronous Timing
Register 1
32 R/W MC_GBASE_ADD. Memory Controller Graphics Base
Address Register
32 R/W MC_DR_ADD. Memory Controller Dirty RAM Address
Register
32 R/W MC_DR_ACC. Memory Controller Dirty RAM Access
Register
Reset Value
248C0040h
00000801h
41104110h
2A733225h
00000000h
00000000h
0000000xh
Revision 3.0
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SC2200.PDF ] | |
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