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PDF SC9500XV Data sheet ( Hoja de datos )
| Número de pieza | SC9500XV | |
| Descripción | XC9500XV Family High-Performance CPLD | |
| Fabricantes | Xilinx Inc | |
| Logotipo |  |
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R XC9500XV Family High-Performance
CPLD
DS049 (v2.0) January 15, 2001
06
Features
• Optimized for high-performance 2.5V systems
- 3.5 ns pin-to-pin logic delays
- Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
- Lower power operation
- Multi-voltage operation
- FastFLASH technology
• Advanced system features
- In-system programmable
- Output banking (XC95144XV, XC95288XV)
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
support on all devices
• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable
gates
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention
• Pin-compatible with 3.3V core XC9500XL family in
common package footprints
• Hot Plugging capability
Advance Product Specification
Family Overview
The XC9500XV family is a 2.5V CPLD family targeted for
high-performance, low-voltage applications in leading-edge
communications and computing systems, where high
device reliability and low power dissipation is important.
Each XC9500XV device supports in-system programming
(ISP) and the full IEEE 1149.1 (JTAG) boundary-scan,
allowing superior debug and design iteration capability for
small form-factor packages. The XC9500XV family is
designed to work closely with the Xilinx Spartan-XL and Vir-
tex FPGA families, allowing system designers to partition
logic optimally between fast interface circuitry and high-den-
sity general purpose logic. As shown in Table 1, logic den-
sity of the XC9500XV devices ranges from 800 to 6400
usable gates with 36 to 288 registers, respectively. Multiple
package options and associated I/O capacity are shown in
Table 2. The XC9500XV family members are fully pin-com-
patible, allowing easy design migration across multiple den-
sity options in a given package footprint.
The XC9500XV architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 3.3V, 2.5V, and 1.8V
inputs, and the outputs may be configured for 3.3V, 2.5V, or
1.8V operation. The XC9500XV device exhibits symmetric
full 2.5V output voltage swing to allow balanced rise and fall
times.
Architecture Description
Each XC9500XV device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide 54
inputs and 18 outputs. The FastCONNECT II switch matrix
connects all FB outputs and input signals to the FB inputs.
For each FB, up to 18 outputs (depending on package
pin-count) and associated output enable signals drive
directly to the IOBs. See Figure 1.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS049 (v2.0) January 15, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
1 page  
R
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in Figure 4, the macrocell register clock
originates from either of three global clocks or a product
XC9500XV Family High-Performance CPLD
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
Product Term Set
Product Term Clock
Product Term Reset
Macrocell
S
D/T
EC
R
I/O/GSR
I/O/GCK1
I/O/GCK2
I/O/GCK3
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
Figure 4: Macrocell Clock and Set/Reset Capability
DS049_04_041400
DS049 (v2.0) January 15, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
5 Page 
R
The input buffer is compatible with 3.3V CMOS, 2.5V
CMOS, and 1.8V CMOS signals. The input buffer uses the
internal 2.5V voltage supply (VCCINT) to ensure that the
input thresholds are constant and do not vary with the
VCCIO voltage. Each input buffer provides input hysteresis
(50 mV typical) to help reduce system noise for input signals
with slow rise or fall edges.
Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
configured for driving either 3.3V, 2.5V, or 1.8V CMOS lev-
els by connecting the device output voltage supply (VCCIO)
to a 3.3V, 2.5V, or 1.8V voltage supply. Figure 11(a) shows
how the XC9500XV device can be used in a 2.5V only sys-
tem.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of
TSLEW) under user control. See Figure 12.
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1”, or always
“0”. There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximum design flexibility.
XC9500XV Family High-Performance CPLD
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
voltage state, as well as provide for additional device
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic Low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
Each IOB also provides for bus-hold circuitry that is active
during valid user operation. The bus-hold feature eliminates
the need to tie unused pins either High or Low by holding
the last known state of the input until the next input signal is
present. The bus-hold circuit drives back the same state via
a nominal resistance (RBH) of 50K ohms. See Figure 13.
Note: The bus-hold output will drive no higher than VCCIO to
prevent overdriving signals when interfacing to 2.5V compo-
nents.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50K ohm pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1K ohm) may be externally
added to any pin to override the default RBH resistance to
force a Low state during power-up or any of these other
modes.
2.5V
2.5V 1.8V 3.3V
3.3V CMOS or
3.3V
0V
2.5V CMOS
2.5V
0V
VCCINT VCCIO1
VCCIO2
XC9500XV
IN
CPLD
OUT
2.5V CMOS
2.5V
0V
GND
3.3V CMOS or
3.3V
0V
2.5V CMOS or
2.5V
0V
1.8V CMOS
1.8V
VCCINT VCCIO1 VCCIO2
OUT1
IN XC9500XV
CPLD
OUT2
GND
1.8V CMOS
1.8V
0V
3.3V CMOS
3.3V
0V
(a) 0V (b)
DS049_11_041400
Figure 11: XC9500XV Devices in (a) 2.5V only and (b) Mixed 3.3V/2.5V/1.8V Systems
DS049 (v2.0) January 15, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SC9500XV.PDF ] | |
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