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PDF SCAN18373T Data sheet ( Hoja de datos )
| Número de pieza | SCAN18373T | |
| Descripción | Transparent Latch with TRI-STATE Outputs | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1998
SCAN18373T
Transparent Latch with TRI-STATE® Outputs
General Description
The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented latch enable and output enable con-
trol signals. This device is compliant with IEEE 1149.1 Stan-
dard Test Access Port and Boundary Scan Architecture with
the incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
n IEEE 1149.1 (JTAG) Compliant
n Buffered active-low latch enable
n TRI-STATE outputs for bus-oriented applications
n 9-bit data busses for parity applications
n Reduced-swing outputs source 24 mA/sink 48 mA
n Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
n TTL compatible inputs
n 25 mil pitch Cerpack packaging
n Includes CLAMP and HIGHZ instructions
n Standard Microcircuit Drawing (SMD) 5962-9311801
Connection Diagram
DS100321-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100321
Pin Names
AI(0–8), BI(0–8)
ALE, BLE
AOE1, BOE1
AO(0–8), BO(0–8)
Description
Data Inputs
Latch Enable Inputs
TRI-STATE Output Enable Inputs
TRI-STATE Latch Outputs
Truth Tables
ALE
X
H
H
L
Inputs
AOE1
H
L
L
L
AI (0–8)
X
L
H
X
Inputs
BLE
X
BOE1
H
BI (0–8)
X
HL
L
HL
H
LL
X
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
AO0 = Previous AO before H-to-L transition of ALE
BO0 = Previous BO before H-to-L transition of BLE
AO (0–8)
Z
L
H
AO0
BO (0–8)
Z
L
H
BO0
Functional Description
The SCAN18373T consists of two sets of nine D-type
latches with TRI-STATE standard outputs. When the Latch
Enable (ALE or BLE) input is HIGH, data on the inputs
(AI(0–8) or BI(0–8) ) enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its input changes. When Latch Enable is LOW, the
latches store the information that was present on the inputs
a set-up time preceding the HIGH-to-LOW transition of the
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1 page  
Description of Boundary-Scan Circuitry (Continued)
Scan Cell TYPE2
DS100321-8
5 www.national.com
5 Page 
AC Electrical Characteristics (Continued)
Scan Test Operation
Symbol
Parameter
VCC
(V)
(Note 10)
tPZL,
tPZH
Propagation Delay
TCK to Data Out
during Update-IR
State
5.0
tPZL,
tPZH
Propagation Delay
TCK to Data Out
during Test Logic
5.0
Reset State
Note 10: Voltage Range 5.0 is 5.0V ±0.5V.
All propagation delays involving TCK are measured from the falling edge of TCK.
Military
TA=−55˚C to +125˚C
CL = 50 pF
Min Max
6.5 26.2
6.5 26.2
7.0 27.4
7.0 27.4
AC Operating Requirements
Scan Test Operation
Symbol
Parameter
tS Setup Time,
Data to TCK (Note 13)
tH Hold Time,
TCK to Data (Note 13)
tS Setup Time, H or L
AOE1, BOE1 to TCK (Note 15)
tH Hold Time, H or L
TCK to AOE1, BOE1 (Note 15)
tS Setup Time, H or L
Internal AOE, BOE,
to TCK (Note 14)
tH Hold Time, H or L
TCK to Internal
AOE, BOE (Note 14)
tS Setup Time
ALE, BLE (Note 12) to TCK
tH Hold Time
TCK to ALE, BLE (Note 12)
tS Setup Time, H or L
TMS to TCK
tH Hold Time, H or L
TCK to TMS
tS Setup Time, H or L
TDI to TCK
tH Hold Time, H or L
TCK to TDI
tW Pulse Width TCK
H
L
fmax Maximum TCK
Clock Frequency
VCC
(V)
(Note 11)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Military
TA = −55˚C to +125˚C
CL = 50 pF
Guaranteed Minimum
3.0
5.5
3.0
4.5
3.0
3.0
3.0
4.0
8.0
2.0
4.0
4.5
12.0
5.0
25
11
Units
Fig.
No.
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Fig.
No.
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| PDF Descargar | [ Datasheet SCAN18373T.PDF ] | |
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