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PDF SAA6579 Data sheet ( Hoja de datos )
| Número de pieza | SAA6579 | |
| Descripción | Radio Data System RDS demodulator | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA6579
Radio Data System (RDS)
demodulator
Product specification
Supersedes data of January 1994
File under Integrated Circuits, IC01
1997 Feb 24
1 page  
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.
SYMBOL
VDDA
VDDD
Vn
Tstg
Tamb
Ves
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pin 12)
voltage on all pins; grounds excluded
storage temperature
operating ambient temperature
electrostatic handling for all pins except
pins 9 and 10
CONDITIONS
note 1
note 2
MIN.
0
0
−0.5
−40
−40
±300
+1 500
MAX.
6
6
VDDX + 0.5
+150
+85
−
−3 000
UNIT
V
V
V
°C
°C
V
V
Notes
1. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
FUNCTIONAL DESCRIPTION
The SAA6579 is a demodulator circuit for RDS
applications. It contains a 57 kHz bandpass filter and a
digital demodulator to regenerate the RDS data stream out
of the multiplex signal (MPX).
Filter part
The MUX signal is band-limited by a second-order
anti-aliasing-filter and fed through a 57 kHz band-pass
filter (8th order band-pass filter with 3 kHz bandwidth) to
separate the RDS signals. This filter uses switched
capacitor technique and is clocked by a clock frequency of
541.5 kHz derived from the 4.332/8.664 MHz crystal
oscillator. Then the signal is fed to the reconstruction filter
to smooth the sampled and filtered RDS signal before it is
output on pin 8. The signal is AC-coupled to the
comparator (pin 7). The comparator is clocked with a
frequency of 228 kHz (synchronized by the 57 kHz of the
demodulator).
Digital part
The synchronous demodulator (Costas loop circuit) with
carrier regeneration demodulates the internal coupled,
digitized signal. The suppressed carrier is recovered from
the two sidebands (Costas loop). The demodulated signal
is low-pass-filtered in such a way that the overall pulse
shape (transmitter and receiver) approaches a
cosinusoidal form in conjunction with the following
Integrate and dump circuit.
The data-spectrum shaping is split into two equal parts and
handled in the transmitter and in the receiver. Ideally, the
data filtering should be equal in both of these parts.
The overall data-channel-spectrum shaping of the
transmitter and the receiver is approximately 100% roll-off.
The Integrate and dump circuit performs an integration
over a clock period. This results in a demodulated and
valid RDS signal in form of biphase symbols being output
from the integrate and dump circuit. The final stages of
RDS data processing are the biphase symbol decoding
and the differential decoding. After synchronization by
data clock RDCL (pin 16) data appears on the RDDA
output (pin 2). The output of the biphase symbol decoder
is evaluated by a special circuit to provide an indication of
good data (QUAL = HIGH) or corrupt data (QUAL = LOW).
Timing
Fixed and variable dividers are applied to the
4.332/8.664 MHz crystal oscillator to generate the
1.1875 kHz RDS clock RDCL, which is synchronized by
the incoming data. Which ever clock edge is considered
(positive or negative going edge) the data will remain valid
for 399 µs after the clock transition. The timing of data
change is 4 µs before a clock change. Which clock
transition (positive or negative going clock) the data
change occurs in, depends on the lock conditions and is
arbitrary (bit slip).
During poor reception it is possible that faults in phase
occur, then the clock signal stays uninterrupted, and data
is constant for 1.5 clock periods. Normally, faults in phase
do not occur on a cyclic basis. If however, faults in phase
occur in this way, the minimum spacing between two
possible faults in phase depends on the data being
transmitted. The minimum spacing cannot be less than
16 clock periods. The quality bit changes only at the time
of a data change.
1997 Feb 24
5
5 Page 
Philips Semiconductors
Radio Data System (RDS) demodulator
Product specification
SAA6579
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Feb 24
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet SAA6579.PDF ] | |
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