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SAA6712E PDF даташит

Спецификация SAA6712E изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «XGA RGB to TFT graphics engine».

Детали детали

Номер произв SAA6712E
Описание XGA RGB to TFT graphics engine
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SAA6712E Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
SAA6712E
XGA RGB to TFT graphics engine
Preliminary specification
File under Integrated Circuits, IC02
1999 Aug 25









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SAA6712E Даташит, Описание, Даташиты
Philips Semiconductors
XGA RGB to TFT graphics engine
Preliminary specification
SAA6712E
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
1.6
2
3
4
5
6
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.6
7.7
7.7.1
7.7.2
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
FEATURES
RGB video input
Video processing
On screen display
Video output
Memory interface
Miscellaneous
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
FUNCTIONAL DESCRIPTION
Data path
System clocks
Input interface clock (VCLK)
Memory interface clock (MCLKI)
I2C-bus interface clock (SCL)
System clock (CLK)
TFT panel clock (PCLK)
RGB input port
TFT output port
Single pixel mode
Double pixel mode
Memory port
SDRAM memory configuration
SGRAM memory configuration
I2C-bus interface
Scaling algorithm
Upscaling
Downscaling
SYSTEM DESCRIPTION
Programming registers
Clock management
Clock generation and multiplexing
Clock divider
RGB input interface
RGB data sampling
Clamp pulse generation
Gain correction pulse generation
8.4
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3
8.7
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.9
8.10
8.10.1
8.10.2
8.10.3
8.11
8.12
8.12.1
8.12.2
8.12.3
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
15
16
17
Video mode and synchronization signal
detection
Memory interface
Memory interface limitations
Initialization of external memory
Frame recovery
Scaling
Downscaling
Upscaling
Upscaler transition function
Panning unit
Overlay port
Overlay insertion
Sync generation
Data sampling
OVCLK gating
Colour correction
On screen display
OSD generals
OSD window
OSD character matrix
Temporal dithering (frame rate controller)
Output interface
General
Frame generation
Timing reference signals
LIMITING VALUES
CHARACTERISTICS
TIMING CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Aug 25
2









No Preview Available !

SAA6712E Даташит, Описание, Даташиты
Philips Semiconductors
XGA RGB to TFT graphics engine
Preliminary specification
SAA6712E
1 FEATURES
1.1 RGB video input
Digital single (24-bit) or dual (48-bit) channel RGB input
Data input of sampled RGB data with a pixel frequency
of maximum 150 MHz
Free definable data acquisition offsets and vertical
window size in single pixel increments, horizontal
window size in double pixel increments
Programmable pulses for ADC clamping and ADC gain
correction
Detection of presence of sync signals, and of their
polarities
Support for auto-adjustment functions for sample clock
frequency, phase, vertical and horizontal sample offset,
as well as colour adjustment
Maximum supported resolution of 1280 × 1024 dots
Super Extended Graphics Adapter (SXGA)
Support for detection of the applied graphics mode
(auto-scan).
1.2 Video processing
Colour correction Look-Up Table (LUT)
Phase correct up and downscaling of the RGB data
Fully programmable scaling ratios
Independent horizontal and vertical scaling engine
Free definable position of the scaled input picture inside
the output picture with programmable border colour.
1.3 On screen display
Character based internal On Screen Display (OSD)
Programmable character matrix sizes of either
24 × 24 pixels (42 characters available) or
12 × 16 pixels (128 characters available)
Programmable width and height of the OSD window,
built from maximum 1152 characters
8 different colours for foreground and background
inclusive transparent colours
Overlay port for external OSD controller.
1.4 Video output
Single pixel/clock (24-bit) or double pixel/clock (48-bit)
digital RGB output
Generation of synchronization and validation signals for
the Thin Film Transistor (TFT) display
Frame rate control (temporal dithering) for displaying
true colour graphics on high colour displays
Free programmable timing for displays of several
manufacturers.
1.5 Memory interface
Support of both 1M × 16 SDRAM, 256k × 32 SGRAM or
128k × 32 SGRAM devices
Maximum memory clock frequency of 125 MHz
Scalable memory size built of either 2, 3 or 4 SDRAM,
or of 1 or 2 SGRAM devices
Special mode for operation without external memory.
1.6 Miscellaneous
Internal Phase-Locked Loop (PLL) for memory and
panel clock generation from the system clock
I2C-bus interface with 2 selectable addresses
Boundary scan test circuit and Joint Test Action Group
(JTAG) test controller
Pin compatible to SAA6721E
Programming compatible to SAA6721E.
1999 Aug 25
3










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Номер в каталогеОписаниеПроизводители
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