PDF SAA6750 Data sheet ( Hoja de datos )

Número de pieza	SAA6750
Descripción	Encoder for MPEG2 image recording EMPIRE
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA6750H Encoder for MPEG2 image recording (EMPIRE) Product speciﬁcation Supersedes data of 1998 Sep 07 File under Integrated Circuits, IC02 2000 May 03 1 page Philips Semiconductors Encoder for MPEG2 image recording (EMPIRE) Product speciﬁcation SAA6750H 3 QUICK REFERENCE DATA SYMBOL VDD IDD(tot) Ptot fVCLK fSCL B VIH VIL VOH VOL Tamb PARAMETER digital supply voltage total digital supply current total power dissipation video clock frequency I2C-bus clock frequency output bit-rate HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage ambient temperature MIN. 3.0 − − 25.6 100 1.5 2.0 −0.5 2.4 − 0 TYP. 3.3 0.22 0.73 27.0 − − − − − − − MAX. UNIT 3.6 V 0.56 A 2.0 W 28.6 MHz 400 kHz 40 Mbit/s 5.5 V +0.8 V VDD V 0.4 V 70 °C 4 ORDERING INFORMATION TYPE NUMBER SAA6750H NAME SQFP208 PACKAGE DESCRIPTION plastic shrink quad ﬂat package; 208 leads (lead length 1.3 mm); body 28 × 28 × 3.4 mm; high stand-off height VERSION SOT316-1 2000 May 03 5 5 Page Philips Semiconductors Encoder for MPEG2 image recording (EMPIRE) Product speciﬁcation SAA6750H SYMBOL VSS TDO TRST TCK TMS VDDCO TDI CS_TEST TEST VDD DATA0 DATA1 DATA2 DATA3 VSS DATA4 DATA5 DATA6 DATA7 VDD VSSCO VDDCO VSSCO VDDCO VSSCO VDDCO VSSCO n.c. DATA8 DATA9 DATA10 DATA11 VSS DATA12 DATA13 PIN INPUT/OUTPUT(1) 157 ground 158 output 159 input 160 input 161 input 162 supply 163 input 164 input 165 input 166 supply 167 input/output 168 input/output 169 input/output 170 input/output 171 ground 172 input/output 173 input/output 174 input/output 175 input/output 176 supply 177 ground 178 supply 179 ground 180 supply 181 ground 182 supply 183 ground 184 − 185 input/output 186 input/output 187 input/output 188 input/output 189 ground 190 input/output 191 input/output Imax (mA) DESCRIPTION − ground for pad ring 3 boundary scan test data output; pin not active during normal operating; with 3-state output; note 3 − boundary scan test reset; pin must be set to LOW for normal operating; with internal pull-up resistor; notes 3 and 4 − boundary scan test clock; pin must be set to LOW during normal operating; with internal pull-up resistor; note 3 − boundary scan test mode select; pin must ﬂoat or set to HIGH during normal operating; with internal pull-up resistor; note 3 − supply voltage for core logic − boundary scan test data input; pin must ﬂoat or set to HIGH during normal operating; with internal pull-up resistor; note 3 − test mode for the internal RAMs; pin must be set to LOW during normal operating − test mode; pin must be set to LOW during normal operating − supply voltage for pad ring 3 DRAM data interface bit 0 (LSB) 3 DRAM data interface bit 1 3 DRAM data interface bit 2 3 DRAM data interface bit 3 − ground for pad ring 3 DRAM data interface bit 4 3 DRAM data interface bit 5 3 DRAM data interface bit 6 3 DRAM data interface bit 7 − supply voltage for pad ring − ground for core logic − supply voltage for core logic − ground for core logic − supply voltage for core logic − ground for core logic − supply voltage for core logic − ground for core logic − reserved pin; do not connect 3 DRAM data interface bit 8 3 DRAM data interface bit 9 3 DRAM data interface bit 10 3 DRAM data interface bit 11 − ground for pad ring 3 DRAM data interface bit 12 3 DRAM data interface bit 13 2000 May 03 11 11 Page

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