DataSheet26.com

SAA6750H PDF даташит

Спецификация SAA6750H изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Encoder for MPEG2 image recording EMPIRE».

Детали детали

Номер произв SAA6750H
Описание Encoder for MPEG2 image recording EMPIRE
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

30 Pages
scroll

No Preview Available !

SAA6750H Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
SAA6750H
Encoder for MPEG2 image
recording (EMPIRE)
Product specification
Supersedes data of 1998 Sep 07
File under Integrated Circuits, IC02
2000 May 03









No Preview Available !

SAA6750H Даташит, Описание, Даташиты
Philips Semiconductors
Encoder for MPEG2 image recording
(EMPIRE)
Product specification
SAA6750H
CONTENTS
1
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
3
4
5
6
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
FEATURES
GENERAL DESCRIPTION
General
Function
Application fields
General
Video editing (PC applications)
Camera signal transmission
Video recording for surveillance
Digital VCR
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Global architecture description
General
Architecture structure
Start-up and operating modes
Start-up requirements
Reset processing
Description of operating modes
Pin behaviour
Video front-end and formatter
General
Data input format
Functional description
Macroblock processor
General
Functional description
Bitstream assembly
General
Pre-packer and packer
Data output port
General
Data output format
Functional description
Application Specific Instruction-set Processor
(ASIP)
General
7.8
7.8.1
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.10
7.10.1
7.10.2
7.10.3
7.11
7.12
7.13
7.14
7.14.1
7.14.2
7.14.3
8
9
10
11
12
13
13.1
13.2
13.3
13.4
13.5
14
15
16
17
Global controller
General
I2C-bus interface and controller
General
Special considerations
I2C-bus data transfer modes
I2C-bus memories and registers
I2C-bus initialization
DRAM interface
General
Application hints
Functional description
FIFO memories
Clock distribution
Input/output levels
Boundary scan test
General
Initialization of boundary scan circuit
Device identification codes
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
2000 May 03
2









No Preview Available !

SAA6750H Даташит, Описание, Даташиты
Philips Semiconductors
Encoder for MPEG2 image recording
(EMPIRE)
Product specification
SAA6750H
1 FEATURES
Digital YUV input according to “ITU-T 601” and
“ITU-T 656”
NTSC and PAL (720 pixels × 480 lines at 60 Hz and
720 pixels × 576 lines at 50 Hz)
Integrated colour conversion 4 : 2 : 2 to 4 : 2 : 0
Integrated format conversion to SIF format (optional)
Real time MPEG2 Simple Profile at Main Level
(SP@ML) encoding
IP frame or I frame only encoding supported
Programmable Group Of Pictures (GOP) size
Integrated motion estimation, half pixel accuracy
Motion compensated noise reduction
Elementary stream data output compliant to MPEG2
standard (“ISO 13818-2”)
Bitstream output compatible to 16-bit parallel interface
with Motorola (68xxx like) protocol style
No external host processor required
4 × 4 Mbit external DRAM required
I2C-bus controlled
Single external video clock 27 MHz
Power supply voltage 3.3 V
Digital inputs 5 V tolerant
Boundary Scan Test (BST) supported.
2 GENERAL DESCRIPTION
2.1 General
The SAA6750H is a new approach towards a stand-alone
MPEG2 video encoder IC. It combines high quality
SP@ML compliant real time encoding with
cost-effectiveness, allowing for the first time the use of an
MPEG2 encoder IC in applications and markets with a
high cost pressure. This has been achieved by means of a
number of innovations in architecture and algorithms
developed by the Philips Research Laboratories, e.g.:
The unique motion estimation algorithm supports highly
efficient encoding by using only I frame and IP frame
mode. B frames need not be used. This leads to a
significantly smaller internal circuitry and also reduces
DRAM memory requirements from at least 4 to 2 Mbyte.
In addition, the absence of B frames simplifies editing of
the compressed data stream.
The patented, motion-compensated temporal noise
filtering which was developed by Philips for professional
equipment reduces noise in the input video before
compression is performed. This technique gives visible
improvements in picture quality, especially in the field of
home recordings with noisy signal sources where this
has proved to be of significant benefit.
Internally the SAA6750H uses a hardware solution for data
compression and a specially developed high performance
processor for control purposes.
2.2 Function
The SAA6750H is a stand-alone single chip video encoder
performing real time MPEG2 compression of digital video
data.
The video data input of the SAA6750H accepts a digital
YUV video data stream in ITU-T 601 format. PAL standard
at 50 Hz and 720 pixels by 576 lines, as well as NTSC at
60 Hz and 720 pixels by 480 lines, are covered. The video
synchronization may either follow ITU-T 656
recommendation or can also be supplied by external
signals. The external reference clock of 27 MHz to
pin VCLK has to be synchronized to the video data. The
product family SAA7111 of Philips Semiconductors
provides a suitable video data stream and reference clock.
Other sources are also supported by the flexible I2C-bus
controlled data input interface of the SAA6750H.
See Section 7.3 for detailed information.
An internal 4 : 2 : 2 to 4 : 2 : 0 colour format conversion is
performed. Optionally, a ITU-T 601 to SIF format
conversion may be activated by the I2C-bus control
settings.
The real time data encoding part of the SAA6750H
combines high-compression rates with high quality picture
performance. This is achieved by the integration of Philips
unique motion estimation algorithm and a patented
motion-compensated noise filtering. The compression
algorithm uses I or IP mode encoding. Normally it selects
automatically the suitable mode but may also be forced to
I mode operating only by the I2C-bus control settings.
2000 May 03
3










Скачать PDF:

[ SAA6750H.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
SAA6750Encoder for MPEG2 image recording EMPIRENXP Semiconductors
NXP Semiconductors
SAA6750HEncoder for MPEG2 image recording EMPIRENXP Semiconductors
NXP Semiconductors

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск