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SAA7111WP PDF даташит

Спецификация SAA7111WP изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Video Input Processor VIP».

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Номер произв SAA7111WP
Описание Video Input Processor VIP
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SAA7111WP Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
SAA7111
Video Input Processor (VIP)
Product specification
Supersedes data of 1996 Oct 30
File under Integrated Circuits, IC22
1998 May 15









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SAA7111WP Даташит, Описание, Даташиты
Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
CONTENTS
1
2
3
4
5
6
7
8
8.1
8.2
8.2.1
8.2.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
9
10
11
12
13
13.1
13.2
14
15
15.1
16
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.2.6
16.2.7
16.2.8
16.2.9
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Analog input processing
Analog control circuits
Clamping
Gain control
Chrominance processing
Luminance processing
RGB matrix
VPO-bus (digital outputs)
Synchronization
Clock generation circuit
Power-on reset and CE input
RTCO output
The Line-21 text slicer
Suggestions for I2C-bus interface of the display
software reading line-21 data
GAIN CHARTS
LIMITING VALUES
CHARACTERISTICS
TIMING DIAGRAMS
CLOCK SYSTEM
Clock generation circuit
Power-on control
OUTPUT FORMATS
APPLICATION INFORMATION
Layout hints
I2C-BUS DESCRIPTION
I2C-bus format
I2C-bus detail
Subaddress 00
Subaddress 02
Subaddress 03
Subaddress 04
Subaddress 05
Subaddress 06
Subaddress 07
Subaddress 08
Subaddress 09
16.2.10
16.2.11
16.2.12
16.2.13
16.2.14
16.2.15
16.2.16
16.2.17
16.2.18
16.2.19
16.2.20
16.2.21
17
17.1
17.2
17.3
18
19
20
20.1
20.2
20.3
20.3.1
20.3.2
20.3.3
20.4
21
22
23
Subaddress 0A
Subaddress 0B
Subaddress 0C
Subaddress 0D
Subaddress 0E
Subaddress 10
Subaddress 11
Subaddress 12
Subaddress 1A (read-only register)
Subaddress 1B (read-only register)
Subaddress 1C (read-only register)
Subaddress 1F (read-only register)
FILTER CURVES
Anti-alias filter curve
Luminance filter curves
Chrominance filter curves
I2C START SET-UP
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
PLCC
QFP
Method (PLCC and QFP)
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 15
2









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SAA7111WP Даташит, Описание, Даташиты
Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
1 FEATURES
Four analog inputs, internal analog source selectors,
e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)
Two analog preprocessing channels
Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel
Switchable white peak control
Two built-in analog anti-aliasing filters
Two 8-bit video CMOS analog-to-digital converters
(ADCs)
On-chip clock generator
Line-locked system clock frequencies
Digital PLL for H-sync processing and clock generation
Requires only one crystal (24.576 MHz) for all standards
Horizontal and vertical sync detection
Automatic detection of 50/60 Hz field frequency and
automatic switching between standards PAL and NTSC
Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43
User programmable luminance peaking or aperture
correction
Cross-colour reduction for NTSC by chrominance comb
filtering
PAL delay line for correcting PAL phase errors
Real time status information output (RTCO)
Brightness Contrast Saturation (BCS) control on-chip
The YUV (CCIR-601) bus supports a data rate of:
– 864 × fH = 13.5 MHz for 625 line sources
– 858 × fH = 13.5 MHz for 525 line sources.
Data output streams for 16, 12 or 8-bit width with the
following formats:
– 411 YUV (12-bit)
– 422 YUV (16-bit)
– 422 YUV [CCIR-656] (8-bit)
– 565 RGB (16-bit) with dither
– 888 RGB (24-bit) with special application.
720 active samples per line on the YUV bus
One user programmable general purpose switch on an
output pin
Built in line-21 text slicer
Power-on control
Two switchable outputs for the digitized CVBS or Y/C
input signals AD1 (7 to 0) and AD2 (7 to 0) via the
I2C-bus
Chip enable function (reset for the clock generator)
Compatible with memory-based features (line-locked
clock)
Boundary scan test circuit complies with the
IEEE Std. 1149.1 1990 (ID-Code = 0 7111 02 B)
I2C-bus controlled (full read-back ability by an external
controller).
2 APPLICATIONS
Desktop video
Multimedia
Digital television
Image processing
Video phone.
3 GENERAL DESCRIPTION
The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).
The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VTR sources. The circuit is I2C-bus controlled.
1998 May 15
3










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