SAA7215HS PDF даташит
Спецификация SAA7215HS изготовлена «NXP Semiconductors» и имеет функцию, называемую «Integrated MPEG AVGD decoders». |
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Детали детали
Номер произв | SAA7215HS |
Описание | Integrated MPEG AVGD decoders |
Производители | NXP Semiconductors |
логотип |
28 Pages
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INTEGRATED CIRCUITS
DATA SHEET
SAA7215; SAA7216; SAA7221
Integrated MPEG AVGD decoders
Preliminary specification
Supersedes data of 1998 Sep 11
File under Integrated Circuits, IC02
2000 Jan 31
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Philips Semiconductors
Integrated MPEG AVGD decoders
Preliminary specification
SAA7215; SAA7216; SAA7221
FEATURES
General features
• Integrated MPEG AVGD decoder: audio, video and
graphics decoding and digital video encoding
• 5 planes display chain: background colour, background
plane, MPEG display plane, graphics plane and cursor
plane
• 16-Mbit or 32-Mbit external Synchronous DRAM
(SDRAM) for MPEG audio and video decoding and
graphics data storage
• Single or double external SDRAM organized as
1 M × 16 or 2 × 1 M × 16 (two independent 16-bit data
bus) interfacing at 81 MHz. Due to efficient memory use
in MPEG decoding, more than 1 Mbit is available for
graphics in the single SDRAM configuration whereas
17 Mbits are available in the double SDRAM
configuration.
• All basic operations of the AVGD decoder are possible
in both 16- and 32-Mbit configuration; enhanced
performance is achieved by the use of 32-Mbit external
SDRAM
• Targeted to BSkyB 3.0 and Canal+ basic box and web
box specifications
• Fast 16-bit data + 22-bit address synchronous or
asynchronous interface with external controller at up to
40.5 MHz
• Dedicated input for compressed audio and video in
Packetized Elementary Stream (PES) or Elementary
Stream (ES) in byte wide or bit serial format.
Accompanying strobe signals distinguish between audio
and video data. Transport stream error correction
available.
• Audio and/or video can also be input via the CPU
interface in PES or ES in 8 or 16-bit parallel format
• Single 27 or 40.5 MHz external clock for time base
reference and internal processing. Internal system time
base at 90 kHz can be synchronized via CPU port.
All required decoding and presentation clocks are
generated internally.
• Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
• Optimum compatibility with T-MIPS controller family
(SAA7214, SAA7219 and successors)
• Boundary scan testing implemented
• External SDRAM self test
• Supply voltage: 3.3 V; package: SQFP208.
CPU related features
• 16-bit data, 22-bit address, Chip Select, Data Strobe
and DaTa ACKnowledge external control protocol
• Fast 16-bit data plus 22-bit address synchronous
interface with the SAA7214, SAA7219 family at up to
40.5 MHz
• Asynchronous interface possible with external
microcontroller
• Support of fast DMA transfer
• Flexible bidirectional interface to external SDRAM
• High speed/low latency interface with second graphics
SDRAM
• Byte access to the full SDRAM in the upper 16-Mbit
address range
• Independent memory mapping of SDRAM and control
registers
• Two programmable independent interrupt lines
available
• Supports Motorola 68xxx interfaces as well as LSI
L64108 interface.
MPEG-2 system features
• Parsing of MPEG-2 PES and MPEG-1 packet streams
• Double system time clock counters
• Stand-alone or supervised audio/video synchronization
• Processing of errors flagged by channel decoding
section.
MPEG-2 video features
• Decoding of MPEG-2 video up to main level, main profile
• Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures. Picture format 720 × 576 at 50 Hz or 720 × 480
at 60 Hz.
• Support of constant and variable bit rates up to
15 Mbits/s for the elementary stream
• Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
• Flexible horizontal scaling from 0.5 up to 4 allows easy
aspect ratio conversion including support for 2.21 : 1
aspect ratio movies; in case of shrinking an anti-aliasing
pre-filter is applied
2000 Jan 31
2
No Preview Available ! |
Philips Semiconductors
Integrated MPEG AVGD decoders
Preliminary specification
SAA7215; SAA7216; SAA7221
• Vertical scaling with fixed factors 0.5, 0.75, 1 or 2;
factor 0.5 realizes picture shrink. Factor 2 can be used
for up-conversion of pictures with 288 (240) lines or
less; factor 0.75 is used for letterbox presentation.
• Horizontal and vertical scaling can be combined to scale
pictures to 1⁄4 of their original size, thus freeing up
screen space for graphic applications like electronic
program guides
• Non full screen MPEG pictures can be displayed in a
box of which position and background colour are
adjustable by the external microcontroller; structured
background is available as part of the graphic features
• Nominal video input buffer size for MP at ML 2.7-Mbit
• Video output may be slaved to internally (master)
generated or externally (slave) supplied
HV synchronization signals or CCIR-656 contained
synchronization signals. The position of active video is
programmable. Display phase is not affected by MPEG
timebase changes.
• Decoding and presentation can be independently
handled under CPU control
• Various trick modes under control of external
microcontroller:
– Freeze field/frame on I- or P-frames; restart on
I-picture
– Freeze field on B-frames; restart at any moment
– Scanning and decoding of I- or I- and P-frames in a
IBP sequence
– Single step mode
– Repeat/skip field for time base correction
– Repeat/skip frame for display parity integrity.
• Synchronization modes: DTS controlled, DTS free
running, software controlled, buffer controlled
• DTS register can be set via external controller;
programmable processing delay compensation.
MPEG-2 audio features
• Supported audio sampling frequencies:
48, 44.1, 32, 24, 22.05 and 16 kHz
• Independent channel volume control and programmable
inter-channel crosstalk through a baseband audio
processing unit
• MPEG audio decoder
– Decoding of 2 channels, layer I and II MPEG-1 audio
and low sampling frequency extension of MPEG-2
– Supports for mono, stereo, intensity stereo and dual
channel mode
– CRC error detection with automatic mute
– Constant and variable bit rates up to 448 kbit/s
– Selectable output channel in dual channel mode
– Storage of last 54 bytes in ancillary data field
– Dynamic range control at output.
• Muting possibility via external controller; automatic
muting in case of errors
• Generation of ‘beeps’ with programmable tone height,
duration and amplitude
• Linear PCM decoding
– Support for up to 8 channels linear PCM elementary
audio streams
– Supports for 8, 16, 20 and 24 bit/sample
– Supports for bit rates up to 6.144 Mbit/s
– 96 kHz LPCM samples will be mapped to a 48 kHz
multi-channel format
– Volume control for linear PCM samples in three
steps: −6, −12 and −18 dB.
• Burst-formatting for interconnection with an external
multi-channel decoder
– AC-3 elementary streams (IEC1937)
– MPEG-2 multi-channel streams in ES or PES format
– Output via the digital audio output or the IEC 958
output.
• Output stage
– Global control for volume and balance
– Serial multi-channel digital audio output with 16, 18,
20 or 22 bits per sample, compatible either to I2S or
Japanese formats; output can be set to high
impedance mode via the external controller
– IEC958 (Serial SPDIF) audio output; output can be
set to high impedance mode
– Clock output 256 or 384 × fs for external
DA converter or clock input; output can be set to high
impedance mode.
• Audio FIFO in external SDRAM; programmable buffer
size, at least 64 kbit is available
• Synchronization modes: PTS controlled, PTS free
running, software controlled, buffer controlled
• PTS register can be set via external controller;
programmable processing delay compensation.
Background colour
• 24 bit YCbCr colour.
2000 Jan 31
3
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