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PDF SAA7335GP Data sheet ( Hoja de datos )
| Número de pieza | SAA7335GP | |
| Descripción | DSP for CD and DVD-ROM systems | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7335
DSP for CD and DVD-ROM
systems
Preliminary specification
File under Integrated Circuits, IC01
1997 Aug 11
1 page  
Philips Semiconductors
DSP for CD and DVD-ROM systems
Preliminary specification
SAA7335
SYMBOL
da1
n.c.
da0
VDDD4
VSSD4
WRi
RDi
ALE
CSi
STOPCLOCK
n.c.
V4
EBUOUT
SYNC
FLAG
DATA
BCLK
WCLK
VDDD5
VSSD5
RAMRW
n.c.
RAMDA7
RAMDA6
RAMDA5
RAMDA4
RAMDA3
RAMDA2
n.c.
RAMDA1
RAMDA0
VDDD6
VSSD6
RAMAD0
RAMAD1
RAMAD2
RAMAD3
RAMAD4
RAMAD5
RAMAD6
VDDD7
1997 Aug 11
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
TYPE
I/O
−
I/O
supply
supply
I
I
I
I
O
−
O
O
O
O
O
I/O
I/O
supply
supply
O
−
I/O
I/O
I/O
I/O
I/O
I/O
−
I/O
I/O
supply
supply
O
O
O
O
O
O
O
supply
DESCRIPTION
sub-CPU data bus bit 1 input/output (parallel)
not connected, reserved
sub-CPU data bus bit 0 input/output (parallel)
digital supply voltage 4
digital ground 4
sub-CPU write enable input (active LOW)
sub-CPU read enable input (active LOW)
sub-CPU address latch enable input
sub-CPU chip select input (active HIGH)
stop clock output
not connected, reserved
serial subcode output (for CD)
digital audio output
I2S-bus sector sync output
I2S-bus correction flag output
I2S-bus serial data output
I2S-bus bit serial clock input/output
I2S-bus word clock input/output
digital supply voltage 5
digital ground 5
RAM read/write control output
not connected, reserved
RAM data bus bit 7 input/output
RAM data bus bit 6 input/output
RAM data bus bit 5 input/output
RAM data bus bit 4 input/output
RAM data bus bit 3 input/output
RAM data bus bit 2 input/output
not connected, reserved
RAM data bus bit 1 input/output
RAM data bus bit 0 input/output
digital supply voltage 6
digital ground 6
RAM address bit 0 output
RAM address bit 1 output
RAM address bit 2 output
RAM address bit 3 output
RAM address bit 4 output
RAM address bit 5 output
RAM address bit 6 output
digital supply voltage 7
5
5 Page 
ADDRESS
BIT
NAME
R/W
DEC HEX
76543 2
1
14 E
MOTOR3 W FIFO set point
MTR_F
R
−
−
−
15 F
MOTO4
W PWM_PDM OVF_SW SW2
reserved
R
−
−
−
16 10 MTR_INTG_L W motor integrator value (7 to 0)
R
17 11 MTR_INTG_H W motor integrator value (15 to 8)
−
SW1
−
−−
motor servo control (3 to 0)
−−
−
−
R
18 12 CLOCKPRE W CL1Div
SUB_C_STAT R ready
19 13 DECMODE W mode
BCLKG_En Div1 (2 to 0)
busy
CRC_OK err (2 to 0)
Mux 2
reserved
Div2 (2 to 0)
cor fail
read TOC
SUB_C_DATA R subcode data (7 to 0)
20 14
reserved
W
−
−
−
−
−
−
SUB_C_End R no meaning (register read used as a signal)
21 15
ANASET W AGC_En gain set gain up
gain down AGC_On reserved
−
FIFOFILL_L R number of C1 frames in FIFO
22 16
VITSET
W slice ON
AdDet ON FEndAutoS
ON
BCA_STAT
R Buff_
Loaded
sync
Buff_ORun
23 17
TACHO1
W tachometer multiplier frequency KTacho (7 to 0)
BCA_DATA
24 18
TACHO2
reserved
25 19
TACHO3
26 1A
27 to 1B to
31 1F
reserved
BCASET
reserved
reserved
R BCA data (7 to 0)
W tachometer interrupt trip frequency tachometer trip (7 to 0)
R− − − − −
W servo control source
Tacho
FRes
Moto2_T3 Fsam
R− − − − −
W BCA_Freq (7 to 0)
R− − − − −
−−−−−
−−
TachoInt_LF
−−
−−
−−
0
−
−
reserved
reserved
−
−
reserved
−
−
−
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7335GP.PDF ] | |
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