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SAA7392HL PDF даташит

Спецификация SAA7392HL изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Channel encoder/decoder CDR60».

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Номер произв SAA7392HL
Описание Channel encoder/decoder CDR60
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SAA7392HL Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
SAA7392
Channel encoder/decoder CDR60
Preliminary specification
File under Integrated Circuits, IC01
2000 Mar 21









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SAA7392HL Даташит, Описание, Даташиты
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
CONTENTS
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
8
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pin description
FUNCTIONAL DESCRIPTION
Microprocessor interfaces
Register map
System clocks
HF analog front-end
Bit recovery
Decoder function
Subcode interface
Digital output
Serial output interface
Motor control
The serial in function
The subcode insert function
The data encoder block
Encode control block
The EFM modulator
The EFM clock generator
The Wobble processor
LIMITING VALUES
9 OPERATING CHARACTERISTICS
9.1 ADC and AGC parameters
10 APPLICATION INFORMATION
10.1 Write start control of encoder in CD-ROM mode
10.2 Write start control of encoder in Audio mode
10.3 Start-up of encode in flow-control operation
10.4 Start-up of encoder in synchronous stream
mode
10.5 Operating CDR60 in CAV mode, flow control
on input stream
10.6 Operating in CLV Mode, Flow Control on Input
Stream
10.7 Operating in CLV Mode, Synchronous Stream
Operation
11 PACKAGE OUTLINE
12 SOLDERING
12.1 Introduction to soldering surface mount
packages
12.2 Reflow soldering
12.3 Wave soldering
12.4 Manual soldering
12.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
13 DEFINITIONS
14 LIFE SUPPORT APPLICATIONS
15 PURCHASE OF PHILIPS I2C COMPONENTS
2000 Mar 21
2









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SAA7392HL Даташит, Описание, Даташиты
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
1 FEATURES
Very high speed Compact Disc (CD) compatible
decoding and encoding device
On-chip Analog-to-Digital Converter (ADC) and
Automatic Gain Control (AGC) for HF data capture
Eight-to-Fourteen Modulation (EFM)
Advanced motor control loop to allow CAV, CLV and
pseudo-CLV playback
Integrated FIFO for de-coupling of mechanism speed
and application speed
Versatile output interface allowing different I2S-bus and
Electronic Industries Association of Japan (EIAJ)
formats
Device is fully compatible with ELM, PLUM and Sanyo
CD-ROM block decoders
Quad-pass CIRC correction for CD mode
(C1-C2-C1-C2)
Subcode/header processing for CD format
Frequency multiplier allows use of a 8 MHz crystal.
2 GENERAL DESCRIPTION
CDR60 is a channel encoder/decoder for
CD/CD-R/CD-RW/CD Audio Recorder systems. It
incorporates all logic and RAM required for the complete
encoding and decoding processes.
There are two main datapaths through the CDR60 device.
The decode datapath captures the incoming EFM data
stream via the HF ADC and AGC functions.
The bit detector recovers the individual bits from the
incoming signal, correcting asymmetry, performing noise
filtering and equalisation, and recovering the channel bit
clock using a digital PLL. The demodulator converts the
EFM bits to byte-wide data symbols, before passing them
onto the decoder for subcode extraction, de-interleaving
and error correction. The decoded data is then made
available via the multi-function serial output interface.
The encode datapath takes data symbols from the block
encoder/decoder via the serial data and subcode input
functions, encoding them via the encoder block. The
encoded data stream is passed to the EFM modulator,
which generates the required EFM signal, output as a
digital bit stream. The encode process is controlled via the
Wobble processor, encode control and EFM clock
generator functions.
As well as these two data processing sections, three
further blocks support overall device operation. The
system clock generator provides all digital clocks required
by the CDR60. The motor servo allows the CDR60 to
control the spindle motor and is controlled by the
microprocessor interface. This interface can be accessed
either via a parallel (80C51) or a serial (I2C-bus) interface.
3 QUICK REFERENCE DATA
SYMBOL
VDDD
VDDA
VDDE
IDD
fxtal
Tamb
Tstg
PARAMETER
supply voltage (core and pad ring)
supply voltage (analog)
supply voltage (output drivers)
supply current
crystal frequency
operating ambient temperature
storage temperature
MIN.
3.0
3.0
3.0
8
0
55
TYP.
3.3
3.3
3.3
200
8.4672
MAX.
3.6
3.6
3.6
33
70
+125
UNIT
V
V
V
mA
MHz
°C
°C
4 ORDERING INFORMATION
TYPE
NUMBER
SAA7392HL
NAME
LQFP80
PACKAGE
DESCRIPTION
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
2000 Mar 21
3
VERSION
SOT315-1










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