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PDF SAB9082 Data sheet ( Hoja de datos )
| Número de pieza | SAB9082 | |
| Descripción | NTSC Picture-In-Picture PIP controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAB9082
NTSC Picture-In-Picture (PIP)
controller
Preliminary specification
Supersedes data of 1999 Feb 18
File under Integrated Circuits, IC02
1999 Nov 12
1 page  
Philips Semiconductors
NTSC Picture-In-Picture (PIP) controller
Preliminary specification
SAB9082
SYMBOL
n.c.
VSSD(RP)
VSSD(T8) and VSSD(T9)
VDDD(P2)
VSSD(P2)
VSSD(D)
VDDD(D)
FBL
PKOFF
DVSYNC
DCLK
SVSYNC
SCL
SDA
POR
VDDA(SA)
VSSA(SA)
VDDA(SF)
SU
Vref(B)(SA)
SV
Vref(T)(SA)
SY
Vbias(SA)
VSSD(SA)
VDDD(SA)
SHSYNC
T6
VDDA(SP)
VSSA(SP)
VSSA(DP)
VDDA(DP)
T7
DHSYNC
VDDD(MA)
VSSD(MA)
Vbias(MA)
MY
Vref(T)(MA)
MV
PIN
52 to 60
61
62 and 63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TYPE
−
S
S
S
S
S
S
O
O
I
I
I
I/O
I/O
I
S
S
S
I
I/O
I
I/O
I
I/O
S
S
I
I/O
S
S
S
S
I/O
I
S
S
I/O
I
I/O
I
DESCRIPTION
not connected
digital ground for memory periphery
digital ground for test
digital supply voltage for periphery
digital ground for periphery
digital ground for digital core
digital supply voltage for digital core
fast blanking control signal output (CMOS levels; +5 V tolerant)
peak off control signal output (CMOS levels; +5 V tolerant)
vertical sync display channel input (CMOS levels; +5 V tolerant)
test clock input (28 MHz; CMOS levels)
vertical sync for subchannel input (CMOS levels; +5 V tolerant)
input/output serial clock (I2C-bus; CMOS levels; +5 V tolerant)
input/output serial data/acknowledge output (I2C-bus; +5 V tolerant)
power-on reset input (CMOS levels; pull-up resistor connected to VDD)
analog supply voltage for subchannel ADCs
analog ground for subchannel ADCs
analog supply voltage for subchannel front-end buffers and clamps
analog U input for subchannel
input/output analog bottom reference voltage for subchannel ADCs
analog V input for subchannel
input/output analog top reference voltage for subchannel ADCs
analog Y input for subchannel
analog bias reference voltage for subchannel ADCs
digital ground for subchannel ADCs
digital supply voltage for subchannel ADCs
horizontal sync input for subchannel (Vi < VSHSYNC)
test data input/output bit 7 (CMOS levels)
analog supply voltage for subchannel PLL
analog ground for subchannel PLL
analog ground for display channel PLL
analog supply voltage for display channel PLL
test data input/output bit 6 (CMOS levels)
horizontal sync input for display channel (Vi < VDHSYNC)
digital supply voltage for main channel ADCs
digital ground for main channel ADCs
analog bias reference voltage for main channel ADCs
analog Y input for main channel
analog top reference voltage for main channel ADCs
analog V input for main channel
1999 Nov 12
5
5 Page 
Philips Semiconductors
NTSC Picture-In-Picture (PIP) controller
Preliminary specification
SAB9082
BGHFP AND BGVFP
These bits control the horizontal and vertical positioning of
the PIP configuration on the screen. The horizontal range
is adjustable in 16 steps of four 28 MHz clock periods.
The vertical range is 16 steps of 1 line/field.
The background colour can be adjusted with bits BSel,
SBBrt and SBCol.
MFIDPON AND SFIDPON
Bits MFidPOn (main field identification position on) and
SFidPOn (subfield identification position on) enable the
field identification position fine tuning. The default value is
off (logic 0), no fine positioning. When on (logic 1), the field
identification position is determined by the value of
MainFidPos and SubFidPos.
SDHFP AND SDVFP
These bytes control the horizontal and vertical positioning
of the subchannel PIPs on the screen. The horizontal
range is 256 steps of eight 28 MHz clock periods.
The vertical range is 256 steps of 1 line/field.
BGON
Bit BGOn determines whether the background is visible.
The background has a size of 720 pixels and 240 lines for
NTSC. The background colour can be adjusted with
bits BSel, SBBrt and SBCol.
MAHFP, SAHFP AND SAVFP
Bits MAHfp<3:0>, bits SAHfp<3:0> and byte SAVfp
control the horizontal and vertical inset starting-points of
the acquired data. The horizontal range is 16 steps of eight
28 MHz clock periods when SV2 is set to logic 1. When
SV2 is set to logic 0, the horizontal range is restricted to
eight steps. The vertical range is 256 steps of 1 line/field.
DUVPOL, DVSPOL, DFPOL AND DHSYNC
These bits control the PLL/deflection settings. With
DUVPol, the polarity of the border UV signals can be
inverted when the deflection circuit after the SAB9082
expects inverted signals. With DVSPol set to logic 0, the
SAB9082 triggers on positive edges of the DVSYNC.
If DVSPol is set to logic 1, it triggers on negative edges.
Bit DFPol can invert the field ID of the incoming fields.
Bit DHsync determines the timing of the DHSYNC pulse.
If it is set to logic 0, a burstkey is expected and if it is set to
logic 1, a horizontal sync is expected at pin DHSYNC.
SUVPOL, SVSPOL, SFPOL AND SHSYNC
These bits control the PLL/decoder settings. With SUVPol,
the polarity of the video UV signals can be inverted when
the decoder circuit before the SAB9082 emits inverted
signals. With SVSPol set to logic 0, the SAB9082 triggers
on positive edges of the SVSYNC. If it is set to logic 1, it
triggers on the negative edges. Bit SFPol can invert the
field ID of the incoming fields. Bit SHsync determines the
timing of the SHSYNC pulse. If it is set to logic 0, a
burstkey is expected and if it is set to logic 1, a horizontal
sync is expected at pin SHSYNC.
BON, SBBRT, SBCOL AND BSEL
Bit BOn can switch the sub-borders on (logic 1) or off
(logic 0). Bits SBBrt<1:0> and SBCol<2:0> set the
brightness and colour type of the selected border.
The brightness is set in four levels of 30%, 50%, 70% and
100% IRE. The colour type is one of black (grey), blue, red,
magenta, green, cyan, yellow or white (grey).For black and
white, a finer scale is available Bits BSel<1:0> select
which colour is set, background or border, see Table 3.
Table 3 BSel modes
BSel<1:0>
00
01
10
11
BORDER COLOUR SET
main
sub
background
sub-border select
MDHFP AND MDVFP
These bytes control the horizontal and vertical positioning
of the main PIP on the screen. The horizontal range is
256 steps of eight 28 MHz clock periods. The vertical
range is 256 steps of 1 line/field.
MHRED
Bits MHRed<5:0>, in a range from 0 to 48, determine the
horizontal reduction factor MHRed/96. If they are set to
logic 0, the PIP is off. If they are set to the maximum value
of 48, the horizontal reduction factor is 0.5.
1999 Nov 12
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SAB9082.PDF ] | |
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