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SAB9083H PDF даташит

Спецификация SAB9083H изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Multistandard Picture-In-Picture PIP controller».

Детали детали

Номер произв SAB9083H
Описание Multistandard Picture-In-Picture PIP controller
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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SAB9083H Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
SAB9083
Multistandard Picture-In-Picture
(PIP) controller
Preliminary specification
Supersedes data of 1999 Feb 18
File under Integrated Circuits, IC02
1999 Nov 12









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SAB9083H Даташит, Описание, Даташиты
Philips Semiconductors
Multistandard Picture-In-Picture (PIP)
controller
Preliminary specification
SAB9083
FEATURES
Double window Picture-In-Picture (PIP) in interlaced or
non-interlaced mode at 8-bit resolution
Internal 1-Mbit DRAM
Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit
performance) with clamp circuit for each acquisition
channel
One PLL which generates the line-locked clocks for the
subchannel
One PLL which generates the line-locked clocks for the
main and display channels
Three 8-bit Digital-to-Analog Converters (DACs)
Linear zoom in both horizontal and vertical directions for
the subchannel
Linear zoom in horizontal direction for the main channel
Three multistandard PIP modes are available.
GENERAL DESCRIPTION
The SAB9083 is a multistandard PIP controller which can
be used in double window applications. The SAB9083
inserts one or two live video signals with reduced size into
another live video signal. The incoming video signals are
expected to be analog baseband signals.
The conversion to the digital environment is done on chip
with ADCs. Processing and storage of the video data is
done entirely in the digital domain. The conversion back to
the analog domain is done by means of DACs. Internal
clocks are generated by PLLs which lock on to the applied
horizontal and vertical syncs.
The main input channel is compressed horizontally by a
factor of two and directly fed to the output. After
compression, a horizontal expansion of two is possible for
the main channel.
The subchannel is also compressed horizontally by a
factor of two but stored in memory before it is fed to the
outputs.
The SAB9083 can also create three multistandard PIP
modes, one with three PIPs placed in a column (MP3) and
two with two columns of three PIPs (MP6, MP6S).
The reduction factors of these PIPs are horizontal 14 and
vertical 13. In the first two modes, the column(s) can be
placed on the left or right side of the screen.
QUICK REFERENCE DATA
SYMBOL
Supply
VDDD
VDDA
IDDD
IDDA
PLL
fclk(sys)
Bloop
tjitter
ζ
PARAMETER
digital supply voltage
analog supply voltage
digital supply current
analog supply current
system clock frequency
loop bandwidth
short term stability
damping factor
CONDITIONS
1792 × fHSYNC
peak-to-peak jitter for 64 µs
MIN. TYP. MAX. UNIT
3.0 3.3 3.6 V
3.0 3.3 3.6 V
50 mA
140 165 210 mA
28 MHz
4 kHz
− − 4 ns
0.7
ORDERING INFORMATION
TYPE NUMBER
SAB9083H
NAME
QFP100
PACKAGE
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
VERSION
SOT317-2
1999 Nov 12
2









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SAB9083H Даташит, Описание, Даташиты
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VSSA(MA) VDDA(DA) VDDD(DA) VSSD(P1) VDDD(RP) VSSD(RL) VDDD(RM) VDDD(P2) VSSD(D) VDDA(SA) VDDA(SF) VDDD(SA)
VDDA(MF) VDDA(MA) VSSA(DA) VSSD(DA) VDDD(P1) VDDD(RL) VSSD(RM) VSSD(RP) VSSD(P2) VDDD(D) VSSA(SA) VSSD(SA)
3 4 5 6 7 14 15 16 17 20 39 40 41 42 61 64 65 66 67 76 77 78 85 86
SU
SV
SY
Vbias(SA)
Vref(T)(SA)
Vref(B)(SA)
79
81
83
84
82
80
CLAMP AND ADC
HORIZONTAL
AND
VERTICAL
FILTER
DAC AND BUFFER
8
10
12
9
11
13
DY
DV
DU
Vbias(DA)
Vref(T)(DA)
Vref(B)(DA)
SHSYNC
SVSYNC
87
72
PLL AND CLOCK
GENERATOR
LINE MEMORY
MU
MY
MV
Vbias(MA)
Vref(T)(MA)
Vref(B)(MA)
2
98
100
97
99
1
CLAMP AND ADC
HORIZONTAL
FILTER
DHSYNC
DVSYNC
94
PLL AND CLOCK
70 GENERATOR
89 90 91 92 95
19
21 to 29, 31,
96 52 to 60
VDDA(SP) VSSA(DP) VDDD(MA)
n.c.
VSSA(SP) VDDA(DP) VSSD(MA)
INTERNAL DRAM
DISPLAY
CONTROL
69
PKOFF
68 FBL
SAB9083
18, 19
2
30
48 to 51
4
62, 63
I2C-BUS
CONTROL
TEST
CONTROL
71
38
32 to 37
6
75 74 73 88 93 44 43 45 46 47
SDA
T6 T7 TM
TCBD TCBR
MGL584
POR
SCL
TCLK TCBC
VSSD(T1)
and
VSSD(T2)
VSSD(T3)
VSSD(T4)
to
VSSD(T7)
VSSD(T8)
and
VSSD(T9)
DCLK
TC
T5 to T0
Fig.1 Block diagram.










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Номер в каталогеОписаниеПроизводители
SAB9083Multistandard Picture-In-Picture PIP controllerNXP Semiconductors
NXP Semiconductors
SAB9083HMultistandard Picture-In-Picture PIP controllerNXP Semiconductors
NXP Semiconductors

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