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NLAS44599DTR2 PDF даташит

Спецификация NLAS44599DTR2 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Low Voltage Single Supply Dual DPDT Analog Switch».

Детали детали

Номер произв NLAS44599DTR2
Описание Low Voltage Single Supply Dual DPDT Analog Switch
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NLAS44599DTR2 Даташит, Описание, Даташиты
NLAS44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS44599 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAS44599 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
Channel Select Input Over−Voltage Tolerant to 5.5 V
Fast Switching and Propagation Speeds
Break−Before−Make Circuitry
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latch−up Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 158 FETs
http://onsemi.com
MARKING
DIAGRAMS
16
1
QFN−16
MN SUFFIX
CASE 485G
AS
4459
ALYW
Current
Part Marking
16
1
C
ALYW
Previous
Part Marking*
*Previous releases of this device may be marked as
shown in this diagram.
16
1
TSSOP−16
DT SUFFIX
CASE 948F
16 9
NLAS
4459
ALYW
18
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 12
1
Publication Order Number:
NLAS44599/D









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NLAS44599DTR2 Даташит, Описание, Даташиты
NC A1
SAB
NO B0
COM B
QFN−16 PACKAGE
16 15 14 13
See TSSOP−16
Switch Configuration
NLAS44599
FUNCTION TABLE
Select AB or CD
On Channel
L NC to COM
H NO to COM
COM D
NO D0
SCD
NC C1
NO A0 1
COM A 2
NC A1 3
SELECT AB 4
NO B0 5
COM B 6
NC B1 7
GND 8
TSSOP−16 PACKAGE
SELECT AB
COM A
16 VCC
15 NC D1
COM B
SELECT CD
COM C
14 COM D
COM D
X1
0/1
2/3
X1
0/1
2/3
0 NO A0
1 NC A1
2 NO B0
3 NC B1
0 NO C0
1 NC C1
2 NO D0
3 NC D1
13 NO D0
Figure 2. IEC Logic Symbol
12 SELECT CD
11 NC C1
10 COM C
9 NO C0
Figure 1. Logic Diagram
http://onsemi.com
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NLAS44599DTR2 Даташит, Описание, Даташиты
NLAS44599
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Positive DC Supply Voltage
VIS Analog Input Voltage (VNO or VCOM)
VIN Digital Select Input Voltage
IIK DC Current, Into or Out of Any Pin
PD Power Dissipation in Still Air
QFN−16
TSSOP−16
*0.5 to )7.0
*0.5 v VIS v VCC )0.5
*0.5 v VI v)7.0
$50
800
450
V
V
mA
mW
TSTG
TL
TJ
MSL
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
*65 to )150
260
+150
Level 1
°C
°C
°C
FR
VESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
UL 94−V0 (0.125 in)
2000
200
1000
V
ILatch−Up
qJA
Latch−Up Performance
Thermal Resistance
Above VCC and Below GND at 125°C (Note 4)
QFN−16
TSSOP−16
$300
80
164
mA
°C/W
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC DC Supply Voltage
VIN Digital Select Input Voltage
VIS Analog Input Voltage (NC, NO, COM)
TA Operating Temperature Range
tr, tf Input Rise or Fall Time, SELECT
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
Min
2.0
GND
GND
*55
0
0
Max
5.5
5.5
VCC
)125
100
20
Unit
V
V
V
°C
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature 5C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100 178,700 20.4
110 79,600
9.4
120 37,000
4.2
130 17,800
2.0
140 8,900
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
1
1 10
100 1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
http://onsemi.com
3










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Номер в каталогеОписаниеПроизводители
NLAS44599DTR2Low Voltage Single Supply Dual DPDT Analog SwitchON Semiconductor
ON Semiconductor
NLAS44599DTR2Low Voltage Single Supply Dual DPDT Analog SwitchON
ON

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