Z80185 PDF даташит
Спецификация Z80185 изготовлена «Zilog.» и имеет функцию, называемую «Z8018x Family MPU». |
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Детали детали
Номер произв | Z80185 |
Описание | Z8018x Family MPU |
Производители | Zilog. |
логотип |
70 Pages
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Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
PRELIMINARY PRODUCT SPECIFICATION
FEATURES
Part
Z80185
Z80195
ROM
(KB)
32 x 8
0
UART
Baud Rate
512 Kbps
512 Kbps
s 100-Pin QFP Package
s 5.0-Volt Operating Range
s Low-Power Consumption
s 0°C to +70°C Temperature Range
Speed
(MHz)
20, 33
20, 33
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
s Enhanced Z8S180 MPU
s Four Z80 CTC Channels
s One Channel ESCC™ Controller
s Two 8-Bit Parallel I/O Ports
s Bidirectional Centronics Interface (IEEE 1284)
s Low-EMI Option
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCC™ serial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
V
CC
GND
V
DD
VSS
DS971850301
1
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Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
Processor
Power Controller
16-Bit Address Bus
8-Bit Data Bus
MMU
DMACs (2)
TxD,
RxD
EMSCC
Parallel Ports (2)
Including IEEE
Bidirectional
Centronics Controller
TOUT
16-Bit Programmable
Reload Timers (2)
UARTs (2)
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Decode
A19-0
/ROMCS
/RAMCS
ROM
32K x 8
(Z80185 Only)
TXA1-0,
RXA1-0
CLK/TRG
CTCs (4)
ZC/TO
Figure 1. Z80185/195 Functional Block Diagram
2 DS971850301
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Zilog
PIN DESCRIPTION
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
/INT1
/INT2
ST
A0
A1
A2
A3
A15
A4
A5
A6
A7
A8
A9
A10
A11
A12
VSS
A13
A14
A16
D0
D1
D2
D3
D4
D5
D6
D7
/RAMCS
100
1
95
90
85 80
5
75
10
70
15 Z80185/Z80195
100-Pin QFP
65
20
60
25
55
30 35 40 45 50
NSTROBE
NACK
NAUTOFD
TOUT//DREQ
BUSY
NINIT
RXA1
/IOCS
TXA1
CKA0/CKS
RXA0
TXA0
/DCD0/CKA1
/CTS0/RXS
/RTS0/TXS
A18
A19
VSS
IEI
/ROMCS
IEO
VSS
/DCD
/CTS
/RTS
/DTR
TXD
/TRXC
RXD
PERROR
Figure 2. 100-Pin QFP Pin Assignments
DS971850301
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DataSheet26.com | 2020 | Контакты | Поиск |