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Z80L182 PDF даташит

Спецификация Z80L182 изготовлена ​​​​«Zilog.» и имеет функцию, называемую «ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP)».

Детали детали

Номер произв Z80L182
Описание ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP)
Производители Zilog.
логотип Zilog. логотип 

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Z80L182 Даташит, Описание, Даташиты
Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY P RODUCT S PECIFICATION
FEATURES
s Z8S180 MPU
- Code Compatible with Zilog Z80®/Z180CPU
- Extended Instructions
- Operating Frequency: 33 MHz/5V or 20 MHz/3.3V
- Two DMA Channels
- On-Chip Wait State Generators
- Two UART Channels
- Two 16-Bit Timer Counters
- On-Chip Interrupt Controller
- On-Chip Clock Oscillator/Generator
- Clocked Serial I/O Port
- Fully Static
- Low EMI Option
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
CONTROLLER (ZIP)
s Two ESCCChannels with 32-Bit CRC
s Three 8-Bit Parallel I/O Ports
s 16550 Compatible MIMIC Interface for
Direct Connection to PC, XT, AT Bus
s 100-Pin Package Styles (QFP, VQFP)
(0.8 Micron CMOS 5120 Technology)
s Individual WSG for RAMCS and ROMCS
GENERAL DESCRIPTION
The Z80182/Z8L182 is a smart peripheral controller IC for
modem (in particular V. Fast applications), fax, voice
messaging and other communications applications. It
uses the Z80180 microprocessor (Z8S180 MPU core)
linked with two channels of the industry standard Z85230
ESCC (Enhanced Serial Communications Controller), 24
bits of parallel I/O, and a 16550 MIMIC for direct connection
to the IBM PC, XT, AT bus.
The Z80182/Z8L182 allows complete flexibility for both
internal PC and external applications. Also current PC
modem software compatibility can be maintained with the
Z80182/Z8L182 ability to mimic the 16550 UART chip. The
Z80180 acts as an interface between the ESCCand
16550 MIMIC interface when used in internal applications,
and between the two ESCC channels in the external
applications. This interface allows data compression and
error correction on outgoing and incoming data. In external
applications, three 8-bit parallel ports are available for
driving LEDs or other devices. Figure 1 shows the Z80182/
Z8L182 block diagram, while the pin assignments for the
QFP and the VQFP packages are shown in Figures 2 and
3, respectively. All references in this document to the
Z80182, or Z182 refer to both the Z80182 and Z8L182.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
V
SS
DS971820600
3-1









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Z80L182 Даташит, Описание, Даташиты
Zilog
PRELIMINARY
GENERAL DESCRIPTION (Continued)
D7-D0
Control
A19-A0
Bus
Transceiver
GLU
Logic
Tx Data
Rx Data
ESCC
Control
85230
ESCC
Channel
A
Z8S180
(Static Z80180)
MPU Core
/TRxCB
85230
ESCC
Channel
B
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
EV1
EV2
/ROMCS
/RAMCS
Address
Decode
16550
MIMIC
Interface
8-Bit Parallel
Port C
8-Bit Parallel
Port B
8-Bit Parallel
Port A
85230
ESCC Ch. A
or Port C
Z180 Signals
or Port B
MUX MUX
MUX
16550 MIMIC
or ESCC
85230 Ch. B
and Port A
Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU
core and "PC side" refers to all interface through the16550 MIMIC interface.
Figure 1. Z80182/Z8L182 Functional Block Diagram
3-2 DS971820600









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Z80L182 Даташит, Описание, Даташиты
Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
/INT0
/INT1/PC6
/INT2/PC7
ST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
VSS
A13
A14
A15
A16
A17
A18/TOUT
VDD
A19
D0
D1
D2
D3
100
1
95
90
85 80
5
75
10
70
15 Z80182/Z8L182
100-Pin QFP
65
20
60
25
55
30 35 40 45 50
/TRXCB/HA0
TXDB//HDDIS
/CTSB//HWR
/DCDB//HRD
TXDA
/TRXCA
RXDA
VDD
IEI
/IOCS/IEO
VSS
/RTXCA
/SYNCA/PC4
/DCDA/PC0
/CTSA/PC1
/MWR/PC2//RTSA
/DTR//REQA/PC3
/W//REQA/PC5
PA7/HD7
PA6/HD6
PA5/HD5
PA4/HD4
PA3/HD3
PA2/HD2
PA1/HD1
PA0/HD0
EV2
EV1
/ROMCS
/RAMCS
DS971820600
Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration
3-3










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