|
|
PDF S1D2502A01-D0B0 Data sheet ( Hoja de datos )
| Número de pieza | S1D2502A01-D0B0 | |
| Descripción | VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de S1D2502A01-D0B0 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
S1D2502A01
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
VIDEO AMP MERGED OSD PROCESSOR
The S1D2502A01 is a very high frequency video amplifier
& wide range OSD processor 1 chip system with I2C Bus
control used in monitors. It contains 3 matched R/G/B video
amplifiers with OSD processor and provides flexible
interfacing to I2C Bus controlled adjustment systems.
32-DIP-600A
FUNCTIONS
• R/G/B video amplifier
• OSD processor
• I2C bus control
• Cut-off brightness control
• R/G/B sub contrast/cut-off control
• Half tone
ORDERING INFORMATION
Device
Package
S1D2502A01-D0B0 32-DIP-600A
Operating Temperature
-20 °C — +75 °C
FEATURES
VIDEO AMP PART
OSD PART
• 3-channel R/G/B video amplifier, 175MHz @f-3dB
• Built in 1K-byte SRAM
• I2C bus control items
• 448 ROM fonts (each font consists of 12 × 18
— Contrast control: -38dB
dots.)
— Sub contrast control for each channel: -12dB
— Brightness control
— OSD contrast control: -38dB
— Cut-off brightness control (AC coupling)
— Cut-off control for each channel (AC coupling)
• Full screen memory architecture
• Wide range PLL available (15kHz — 96kHz,
Reference 800 X 600)
• Programmable vertical height of character
— Switch registers for SBLK and video half tone and • Programmable vertical and horizontal
CLP/BLK polarity selection and INT/EXT CLP selection positioning
and generated CLP width control
• Character color selection up to 16 different
• Built in ABL (automatic beam limitation)
colors
• Built in video input clamp, BRT clamp
• Built in video half tone (3mode) function on OSD
pictures
• Programmable background color (up to 16
colors)
• Character blinking, bordering and shadowing
• Capable of 8.0Vp-p output swing
• Color blinking
• Improvement of rise & fall time (2.2ns)
• Character scrolling
• Cut-off brightness control
• Fade-in and fade-out
• Built in blank gate with spot killer
• Box drawing
• Clamp pulse generator
• Character sizing up to four times
• OSD intensity
• BLK, CLP polarity selection
• 76.8MHz pixel frequency from on-chip PLL
(Reference 800 X 600)
• Clamp gate with anti OSD sagging
0
1 page  
S1D2502A01
PIN DESCRIPTION
Pin No
1
32
3
4
5
Pin Name
VFLB
HFLB
VCO_IN_P
VPEF/
VREF
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Table 2. Pin Description
Schematic
VFLB
HFLB
Description
FLB signal is in TTL level
Multi polarity input
PLL loop filter output
BandGap ref. output
7 Contrast cap
(CONT_CAP)
Contrast cap range
(0.1uF — 5uF)
I2C Data
4.0K
Vref
100µA
8 ABL_IN
VCC
100K
2K
Vref
ABL input DC range
(1 — 4.5V)
Vref
250µA
4
5 Page 
S1D2502A01
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = VDDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors =
470Ω, Vin
otherwise
= 0.7Vpp manually
stated (see 12))
adjust
video
output
pins
18,
21
and
24
to
4V
DC
for
the
AC
test
(see
11)
unless
Table 6. AC Electrical Characteristics
Parameter
Contrast max. output voltage
Contrast max. output channel difference
Contrast center output voltage
Contrast center output channel difference
Contrast max. - Center attenuation
Sub contrast center output voltage
Sub contrast center output channel
difference
Sub contrast min. output voltage
Sub contrast min. output channel difference
Sub contrast max. - min. attenuation
ABL control range
R/G/B video rising time (see 7)
R/G/B video falling time (see 7)
R/G/B blank output rising time (see 7)
R/G/B blank output falling time (see 7)
R/G/B video band width (see 7, 8)
Video AMP 50MHz cross talk
Symbol
Vcff
∆ Vcff
Vc80
∆ Vc80
C
Vd80
∆ Vd80
Vd00
∆ Vd00
D
ABL
tr (video)
tf (video)
tr (blank)
tf (blank)
f (-3dB)
CT_50M
(see7, 9)
Conditions
03, 05, 06, 07 = FFH
04, 08 — 0C = 80H
RGB input = S1
03, 04, 08 ~ 0C = 80H
05, 06, 07 = FFH
RGB input = S1
C = 20log (Vc80/Vcff)
03 = FFH
04 — 0C = 80H
RGB input = S1
Min
5.0
∆ 10
2.5
∆ 10
-8
2.3
∆ 10
03 = FFH, 05—07: 00H
04, 08 — 0C = 80H
RGB input = S1
D = 20log (Vd00/Vcff)
(see 15)
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
RGB input = S2
POR
HFLB: S4
1.3
∆ 10
-14
-12
-
-
-
-
(see 16)
175
(see 17)
-
Value
Typ
5.7
-
2.85
-
-6
2.6
-
1.6
-
-12
-10
2.2
2.2
6.0
8.0
-
-25
Max
6.4
-
3.2
-
-4
2.9
-
1.9
-
-10
-8
2.8
2.8
12.0
15.0
-
-20
Unit
Vpp
%
Vpp
%
dB
Vpp
%
Vpp
%
dB
dB
ns
ns
ns
ns
MHz
dB
Video AMP 130MHz cross talk
Absolute gain match
Gain change between amplifier
CT_130M
(see7, 9)
(see 18)
Avmatch (see 6)
Avtrack (see 7)
- -15 -10 dB
-1 - 1 dB
-1 - 1 dB
10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S1D2502A01-D0B0.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| S1D2502A01-D0B0 | VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS | Samsung semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |