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S2060B PDF даташит

Спецификация S2060B изготовлена ​​​​«ETC» и имеет функцию, называемую «GIGABIT ETHERNET TRANSCEIVER».

Детали детали

Номер произв S2060B
Описание GIGABIT ETHERNET TRANSCEIVER
Производители ETC
логотип ETC логотип 

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S2060B Даташит, Описание, Даташиты
DEVICE
SGPIEGCAIFBICITATEIOTNHERNET TRANSCEIVER
GIGABIT ETHERNET TRANSCEIVER
FEATURES
• Operating rate
• 1250 MHz (Gigabit Ethernet) line rates
• Half and full VCO output rates
• Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
• Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
• Receiver PLL provides clock and data recovery
• 10-bit parallel TTL compatible interface
• Low-jitter serial LVPECL compatible interface
• Local loopback
• Single +3.3 V supply, 620 mW power dissipation
• 64 PQFP or TQFP package
• Continuous downstream clocking from receiver
• Drives 30 m of Twinax cable directly
APPLICATIONS
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
®
S2060
S2060
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
Gigabit
Ethernet
Controller
S2060
Optical
Tx
Optical
Rx
Optical
Rx
Optical
Tx
S2060
Gigabit
Ethernet
Controller
March 7, 2001 / Revision H
1









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S2060B Даташит, Описание, Даташиты
S2060
S2060 OVERVIEW
The S2060 transmitter and receiver provide serial-
ization and deserialization functions for block en-
coded data to implement a Gigabit Ethernet
interface. The S2060 functional block diagram is de-
picted in Figure 2. The sequence of operations is as
follows:
Transmitter
1.10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data input to the S2060 should be
from a DC-balanced encoding scheme, such as the
8B/10B transmission code, in which information to be
transmitted is encoded 8 bits at a time into 10-bit trans-
GIGABIT ETHERNET TRANSCEIVER
mission characters1. For reference, Table 1 shows the
mapping of the parallel data to the 8B/10B codes.
Loop Back
Local loopback provides a capability for performing
off-line testing. This is useful for ensuring the integ-
rity of the serial channel before enabling the trans-
mission medium. It also allows for system
diagnostics.
1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC 9391, May 1982.
Table 1. Data Mapping to 8B/10B
Alphabetic Representation
Data Byte
TX[0:9] or RX[0:9] 0 1 2 3 4 5 6 7 8 9
8B/10B
Alphabetic Representation
a
b
c
d
e
i
f
gh
j
Figure 2. Functional Block Diagram
TX[0:9]
10 FIFO
(4 x 10)
10
TBC
PLL Clock
Multiplier w/
lock detect
F0 = F1 x 10
Shift
Register
S2060
TXP
TXN
RATEN
RXP
RXN
EWRAP
-LCK_REF
EN_CDET
PLL Clock
2:1 Recovery w/
lock detect
Control
Logic
D
Shift
Register
10
DQ
RX[0:9]
COMMA
Detect
Logic
COM_DET
RBC0
RBC1
2 March 7, 2001 / Revision H









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S2060B Даташит, Описание, Даташиты
GIGABIT ETHERNET TRANSCEIVER
TRANSMITTER DESCRIPTION
The S2060 transmitter accepts 10-bit parallel input
data and serializes it for transmission over fiber optic
or coaxial cable media. The chip is fully compatible
with the IEEE 802.3z Gigabit Ethernet standard, and
supports the Gigabit Ethernet data rate of 1250.0
Mbps. The S2060 uses a PLL to generate the serial
rate transmit clock. The transmitter runs at 10 times
the TBC input clock, and operates in either full rate
or half rate mode. At the full VCO rate the transmitter
runs at 1.25 GHz, while in half rate mode it operates
at 625 MHz.
Parallel-to-Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the trans-
mitter on the positive going edge of TBC. The data is
then clocked into the serial output shift register. The
shift register is clocked by the internally generated
bit clock which is 10x the TBC input frequency. TX[0]
is transmitted first.
S2060
Transmit Byte Clock (TBC)
The Transmit Byte Clock input (TBC) must be sup-
plied from a clock source with 100 ppm tolerance to
assure that the transmitted data meets the Gigabit
Ethernet frequency limits. The internal serial clock is
frequency locked to TBC (125.00 MHz).
TBC may be 62.5 MHz or 125 MHz, determined by
the state of the RATEN input. Operating rates are
shown in Table 2.
Transmit Latency
The average transmit latency is 4 byte times.
Table 2. Operating Rates
RATEN
Parallel Input TBC Frequency
Rate (Mbps)
(MHz)
0 125
125
1 62.5
62.5
Serial Output
Rate (Gbps)
1.25
0.625
March 7, 2001 / Revision H
3










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