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PDF W167B Data sheet ( Hoja de datos )
| Número de pieza | W167B | |
| Descripción | 133-MHz Spread Spectrum FTG for Pentium II Platforms | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU outputs selectable frequency
• Three copies of 3V66 selectable frequency output at
3.3V
• Ten copies of PCI clocks (selectable frequency), 3.3V
• One double strength 14.318-MHz reference output at
3.3V
• One copy of 48-MHz USB clock
• One copy of selectable 24-/48-MHz for SIO
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Three copies of IOAPIC
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V±5%
VDDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
X1 XTAL
X2 OSC
VDDQ3
REF2X
VDDQ2
CPU_[0:2]
3
SEL133/100#
PLL 1
÷2
÷2/÷1.5
PWRDWN#
Power
Down
Logic
÷2
÷2
SDATA
SCLK
PLL2
Serial
Logic
÷2
CPUdiv2
VDDQ3
3V66_[0:2]
3
PCI0/SEL2*
PCI1/SEL1*
PCI_[2:9]
8
VDDQ2
IOAPIC[0:2]
3
QVD# DQ3
48MHz/SEL0*
SIO/24_48#MHz
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/
CPU 3V66 PCI IOAPIC
100# SEL2 SEL1 SEL0 MHz MHz MHz MHz
1 1 1 1 133.3 66.7 33.3 16.7
1 1 1 0 138 69 34.5 17.3
1 1 0 1 143 71.5 35.8 17.9
1 1 0 0 148 74 37 18.5
1 0 1 1 150 75 37.5 18.8
1 0 1 0 152.5 76.3 38.1 19.1
1 0 0 1 155 77.5 38.8 19.4
1 0 0 0 160 80 40 20
0 1 1 1 100.2 66.8 33.4 16.7
0 1 1 0 105 70 35 17.5
0 1 0 1 114 76 38 19
0 1 0 0 120 80 40 20
0 0 1 1 66.8 66.8 33.4 16.7
0 0 1 0 124 82.7 41.3 20.7
0 0 0 1 128.5 64.3 32.1 16.1
0 0 0 0 133.9 67 33.5 16.7
Pin Configuration[1]
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 VDDQ2
46 IOAPIC0
45 IOAPIC1
44 GND
43 VDDQ2
42 CPUdiv2
41 GND
40 VDDQ2
39 CPU2
38 GND
37 VDDQ2
36 CPU1
35 CPU0
34 SDATA
33 VDDQ3
32 GND
31 PWRDN#*
30 SCLK
29 VDDQ3
28 SIO/24_48#MHz*
27 48MHz/SEL0*
26 GND
25 SEL133/100#
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999
1 page  
PRELIMINARY
W167B
Spread Spectrum Feature
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread. Figure 4
details the Cypress spreading pattern. Cypress does offer op-
tions with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Figure 3. Typical Clock and SSFTG Comparison
Time
Figure 4. Typical Modulation Profile
5
5 Page 
PRELIMINARY
W167B
Signaling Requirements
As shown in Figure 6, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a “start bit” as shown in Figure
7. A “stop bit” signifies that a transmission has ended.
As stated previously, the W167B sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 8.
Sending Data to the W167B
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Figure 7. Serial Data Bus Start and Stop Bit
Stop
Bit
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet W167B.PDF ] | |
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