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W49F201T-55 PDF даташит

Спецификация W49F201T-55 изготовлена ​​​​«Winbond» и имеет функцию, называемую «128K X 16 CMOS FLASH MEMORY».

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Номер произв W49F201T-55
Описание 128K X 16 CMOS FLASH MEMORY
Производители Winbond
логотип Winbond логотип 

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W49F201T-55 Даташит, Описание, Даташиты
Preliminary W49F201
128K × 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K × 16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F201 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read/Erase/Program
Fast Program operation:
Word-by-Word programming: 50 µS (max.)
Fast Erase operation: 60 mS (typ.)
Fast Read access time: 45/55 nS
Endurance: 1K/10K cycles (typ.)
Ten-year data retention
Hardware data protection
Sector configuration
One 8K words boot block with lockout
protection
Two 8K words parameter blocks
One 104K words (208K bytes) Main Memory
Array Blocks
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 44-pin SOP, 48-pin TSOP
Publication Release Date: June 1999
- 1 - Revision A1









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W49F201T-55 Даташит, Описание, Даташиты
Preliminary W49F201
PIN CONFIGURATIONS
BLOCK DIAGRAM
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
44-pin
SOP
48-pin
TSOP
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 NC
32 GND
31 DQ15
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
48 A16
47 NC
746 GND
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 GND
26 CE
25 A0
VDD
VSS
CE
OE
WE
RESET
CONTROL
A0
. DECODER
.
A16
OUTPUT
BUFFER
DQ0
..
DQ15
MAIN MEMORY
104K WORDS
PARAMETER
BLOCK2
8K WORDS
PARAMETER
BLOCK1
8K WORDS
BOOT BLOCK
8K WORDS
1FFFF
06000
05FFF
04000
03FFF
02000
01FFF
00000
PIN DESCRIPTION
SYMBOL
RESET
A0A16
DQ0DQ15
CE
OE
WE
VDD
GND
NC
PIN NAME
Reset
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
-2-









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W49F201T-55 Даташит, Описание, Даташиты
Preliminary W49F201
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer
to the timing waveforms for further details.
Reset Operation
The RESET input pin can be used in some application. When RESET pin is at high state, the device
is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts
the device and all outputs are at high impedance state. The device also resets the internal state
machine to read array data. The operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence to assure data integrity. As the high state re-asserted
to the RESET pin, the device will return to read or standby mode, it depends on the control signals.
The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin
is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be
reprogrammed even though the boot block lockout function is enabled.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method.
There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the
lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once
the RESET pin returns to TTL level, the lockout feature will be activated again.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the
output data in DQ0 is "0", the lockout feature is inactivated and the block can be
erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
Publication Release Date: June 1999
- 3 - Revision A1










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