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W49L102Q-55B PDF даташит

Спецификация W49L102Q-55B изготовлена ​​​​«Winbond» и имеет функцию, называемую «64K X 16 CMOS 3.3V FLASH MEMORY».

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Номер произв W49L102Q-55B
Описание 64K X 16 CMOS 3.3V FLASH MEMORY
Производители Winbond
логотип Winbond логотип 

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W49L102Q-55B Даташит, Описание, Даташиты
Preliminary W49L102
64K × 16 CMOS 3.3V FLASH MEMORY
GENERAL DESCRIPTION
The W49L102 is a 1-megabit, 3.3-volt only CMOS flash memory organized as 64K × 16 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49L102 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 3.3-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 3.3-volt operations:
3.3-volt Read
3.3-volt Erase
3.3-volt Program
Fast Program operation:
Word-by-Word programming: 50 µS (max.)
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 55/70/90 nS
Endurance: 1K/10K cycles (typ.)
Twenty-year data retention
Hardware data protection
8K word Boot Block with Lockout protection
Low power consumption
Active current: 15 mA (typ.)
Standby current: 10 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 40-pin TSOP and 44-pin
PLCC
Publication Release Date: June 1999
- 1 - Revision A1









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W49L102Q-55B Даташит, Описание, Даташиты
Preliminary W49L102
PIN CONFIGURATIONS
BLOCK DIAGRAM
A9
A10
A11
A12
A13
A14
A15
NC
WE
VDD
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-pin
TSOP
40 GND
39 A8
38 A7
37 A6
36 A5
35 A4
34 A3
33 A2
32 A1
31 A0
30 OE
29 DQ0
28 DQ1
27 DQ2
26 DQ3
25 DQ4
24 DQ5
23 DQ6
22 DQ7
21 GND
D DD/
V/
AA
Q Q Q C N N D WN 1 1
13 14 15 E C C D E C 5 4
DQ12
DQ11
DQ10
DQ9
DQ8
GND
NC
DQ7
DQ6
DQ5
DQ4
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 44-pin 35
12
PLCC
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
D DDD / N A A A A A
Q QQQ O C 0 1 2 3 4
3 210 E
VDD
VSS
CE
OE CONTROL
WE
OUTPUT
BUFFER
DQ0
.
.
DQ15
A0
.
DECODER
.
A15
MAIN
MEMORY
(56K Words)
BootBlock
(8K Words)
PIN DESCRIPTION
SYMBOL
A0A15
DQ0DQ15
CE
OE
WE
VDD
GND
NC
PIN NAME
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
-2-









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W49L102Q-55B Даташит, Описание, Даташиты
Preliminary W49L102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49L102 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is
de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block can not be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will only affect the main memory.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the
output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Input Levels
While operating with a 3.0V3.6V power supply, the address inputs and control inputs (OE, CE and
WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to 3.6V.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the main
memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as
before the chip erase operation). The entire memory array (main memory and boot block) will be
erased to FF hex. by the chip erase operation if the boot block programming lockout feature is not
activated. The device will automatically return to normal read mode after the erase operation
completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Main Memory Erase Operation
The main memory erase mode can be initiated by a six-word command sequence. After the
command loading cycle, the device enters the internal main-memory erase mode, which is
automatically timed and will be completed in a fast 100 mS (typical). The host system is not required
Publication Release Date: June 1999
- 3 - Revision A1










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Номер в каталогеОписаниеПроизводители
W49L102Q-5564K X 16 CMOS 3.3V FLASH MEMORYWinbond
Winbond
W49L102Q-55B64K X 16 CMOS 3.3V FLASH MEMORYWinbond
Winbond

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